Cypress enCoRe V CY7C643 Series Technical Reference Manual Download Page 211 | Manualshive

Page: 211 / 257

background image

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H

211

x,FFh

21.3.44 CPU_SCR0

System Status and Control Register 0

This register is used to convey the status and control of events for various functions of a enCoRe V device.

In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits
must always be written with a value of ‘0’. For additional information, refer to the

Register Definitions on page 116

in the Sys-

tem Resets chapter.

7

GIES

Global Interrupt Enable Status. It is recommended that the user read the Global Interrupt Enable Flag
bit from the

CPU_F register on page 208

. This bit is read only for GIES. Its use is discouraged, as the

Flag register is now readable at address x,F7h (read only).

5

WDRS

Watchdog Reset Status. This bit may not be set by user code; however, it may be cleared by writing
a ‘0’.
0

No watchdog reset has occurred.

1

Watchdog reset has occurred.

4

PORS

Power-On-Reset Status. This bit may not be set by user code; however, it may be cleared by writing
a ‘0’.
0

Power-on-reset has not occurred and watchdog timer is enabled.

1

Is set after external reset or power-on-reset.

3

Sleep

Set by the user to enable the CPU sleep state. CPU remains in Sleep mode until any interrupt is
pending.
0

Normal operation.

1

Sleep.

0

STOP

0

M8C is free to execute code.

1

M8C is halted and is only cleared by POR, XRES, or WDR.

Individual Register Names and Addresses:

x,FFh

CPU_SCR0 : x,FFh

7

6

5

4

3

2

1

0

Access : POR

R : 0

RC : 0

RC : 1

RW : 0

RW : 0

Bit Name

GIES

WDRS

PORS

Sleep

STOP

Bit

Name

Description

«
...
209
210
211
212
213
...
»

Summary of Contents for enCoRe V CY7C643 Series

Page 1: ...enCoRe V CY7C643xx enCoRe V LV CY7C604xx Technical Reference Manual TRM Document No 001 32519 Rev H November 19 2018 Cypress Semiconductor 198 Champion Court San Jose CA 95134 1709 www cypress com...

Page 2: ...HANTABILITY AND FITNESS FOR A PARTICULAR PUR POSE To the extent permitted by applicable law Cypress reserves the right to make changes to this document without fur ther notice Cypress does not assume...

Page 3: ...V OCD 48 Pin Part Pinout20 1 1 7 32 Pin QFN with USB 21 1 1 8 48 Pin SSOP 22 Section B enCoRe V Core 23 2 CPU Core M8C 26 2 1 Overview 26 2 2 Internal Registers 26 2 3 Address Spaces 26 2 4 Instructio...

Page 4: ...5 3 8 INT_VC Register 51 5 3 9 Related Registers 51 6 General Purpose I O GPIO 52 6 1 Architectural Description 52 6 1 1 General Description 53 6 1 2 Digital I O 53 6 1 3 Analog and Digital Inputs 53...

Page 5: ...on 70 8 12 Wounding 70 8 13 On Chip Debugger Modes 70 8 14 Test Modes 70 8 15 Power Modes 70 8 16 Design Flow 70 8 17 Operating Condition Requirements 71 8 18 DC Specifications 71 8 19 AC Specificatio...

Page 6: ...90 13 1 Architectural Description 90 13 2 Register Definitions 91 13 2 1 MUX_CRx Registers 91 Section C System Resources 92 14 Digital Clocks 96 14 1 Architectural Description 96 14 1 1 Internal Main...

Page 7: ...n 121 17 2 Register Definitions 122 17 2 1 VLT_CR Register 122 17 2 2 VLT_CMP Register 122 18 SPI 123 18 1 Architectural Description 123 18 1 1 SPI Protocol Function 123 18 1 2 SPI Master Function 124...

Page 8: ...4 USBIO_CR1 Register 148 20 3 5 EP0_CR Register 149 20 3 6 EP0_CNT Register 150 20 3 7 EP0_DRx Register 150 20 3 8 EPx_CNT1 Register 151 20 3 9 EPx_CNT0 Register 152 20 3 10 EPx_CR0 Register 153 20 3...

Page 9: ...ions have an introduction an archi tectural application description register definitions and timing diagrams The sections are as follows Overview Presents the top level architecture helpful informatio...

Page 10: ...The CPU core called the M8C is a powerful processor with speeds up to 24 MHz The M8C is a four MIPS 8 bit Harvard architecture microprocessor Within the CPU core are the SROM and Flash memory componen...

Page 11: ...o re M 8 C S u p e rviso ry R O M S R O M 8 K 1 6 K 3 2 K F la sh N o n vo la tile M e m o ry S Y S T E M R E S O U R C E S S Y S T E M B U S A n a lo g R e fe re n ce S Y S T E M B U S P o rt 3 P o...

Page 12: ...s are available from the following distributors Digi Key Avnet Arrow and Future The Cypress Online Store contains development kits C compilers and all accessories for enCoRe V development Go to the Cy...

Page 13: ...10100b or 01000011b Numbers not indicated by an h or b are decimal Units of Measure This table lists the units of measure used in this manual Register Conventions Convention Example Description x in a...

Page 14: ...ISR interrupt service routine ISSP in system serial programming IVR interrupt vector read LRb last received bit LRB last received byte LSb least significant bit LSB least significant byte MISO master...

Page 15: ...of Dig ital I O 1 1 1 CY7C60413 enCoRe V LV 16 Pin Part Pinout Table 1 1 16 Pin QFN COL Part Pinout Pin No Type Name Description Devices Digital Analog 1 IO I P2 5 XTAL Out 2 IO I P2 3 XTAL In 3 IOHR...

Page 16: ...down 18 IO I P3 0 19 IO I P3 2 20 IO I P2 0 21 IO I P2 2 22 IO I P2 4 23 IO I P2 6 24 IOH I P0 0 25 IOH I P0 2 26 IOH I P0 4 27 IOH I P0 6 28 Power Vdd Power pin 29 IOH I P0 7 30 IOH I P0 5 31 IOH I P...

Page 17: ...l down 18 IO I P3 0 19 IO I P3 2 20 IO I P2 0 21 IO I P2 2 22 IO I P2 4 23 IO I P2 6 24 IOH I P0 0 25 IOH I P0 2 26 IOH I P0 4 27 IOH I P0 6 28 Power Vdd Power pin 29 IOH I P0 7 30 IOH I P0 5 31 IOH I...

Page 18: ...3 4 30 IO I P3 6 Pin No Digital Analog Name Description 31 IO I P4 0 32 IO I P4 2 33 IO I P2 0 41 Power Vdd Power pin 34 IO I P2 2 42 NC No connection 35 IO I P2 4 43 NC No connection 36 IO I P2 6 44...

Page 19: ...31 IO I P4 0 32 IO I P4 2 Pin No Digital Analog Name Description 33 IO I P2 0 41 Power Vdd Power pin 34 IO I P2 2 42 NC No connection 35 IO I P2 4 43 NC No connection 36 IO I P2 6 44 IOH I P0 7 37 IOH...

Page 20: ...rt 24 IOHR I P1 4 EXTCLK 25 IOHR I P1 6 26 Input XRES Active high external reset with internal pull down 27 IO I P3 0 28 IO I P3 2 29 IO I P3 4 30 IO I P3 6 31 IO I P4 0 32 IO I P4 2 Pin No Digital An...

Page 21: ...ng Input 32 Power VSS Ground Pin Legend A Analog I Input O Output OH 5 mA High Output Drive R Regulated Output 1 On power up the SDA P1 0 drives a strong high for 256 sleep clock cycles and drives res...

Page 22: ...No connection 42 I O I P2 4 35 XRES Active high external reset with internal pull down 43 I O I P2 6 36 I O I P3 0 44 IOH I P0 0 37 I O I P3 2 45 IOH I P0 2 38 I O I P3 4 46 IOH I P0 4 39 I O I P3 6...

Page 23: ...visory ROM SROM on page 32 RAM Paging on page 38 Interrupt Controller on page 44 General Purpose I O GPIO on page 52 Internal Main Oscillator IMO on page 67 Internal Low speed Oscillator ILO on page 7...

Page 24: ...eserved Reserved V Monitor RW 00 0 DBh INT_CLR1 Endpoint3 Endpoint2 Endpoint1 Endpoint0 USB SOF USB Bus Rst Timer2 Timer1 RW 00 0 DCh INT_CLR2 USB_WAKE Endpoint8 Endpoint7 Endpoint6 Endpoint5 Endpoint...

Page 25: ...0 RW 07 1 D3h ECO_TRIM ECO_XGM 2 0 ECO_LP 1 0 RW 00 1 E1h ECO_CFG ECO_LPM ECO_EXW ECO_EX RW 00 SLEEP AND WATCHDOG REGISTERS page 82 0 E3h RES_WDT WDSL_Clear 7 0 W 00 1 EBh SLP_CFG PSSDC 1 0 RW 0 1 EC...

Page 26: ...byte in the stack is at address FFh the stack pointer wraps to RAM address 00h It is the firmware developer s responsibility to ensure that the stack does not overlap with user defined variables in R...

Page 27: ...A C Z 11 4 2 SUB A expr C Z 3E 10 2 MVI A expr Z 6B 7 2 RLC expr C Z 12 6 2 SUB A expr C Z 3F 10 2 MVI expr A 6C 8 2 RLC X expr C Z 13 7 2 SUB A X expr C Z 40 4 1 NOP 6D 4 1 RRC A C Z 14 7 2 SUB expr...

Page 28: ...expr 11 4 2 SUB A expr C Z 70 4 2 AND F expr C Z 5A 5 2 MOV expr X 12 6 2 SUB A expr C Z 41 9 3 AND reg expr expr Z 5B 4 1 MOV A X Z 13 7 2 SUB A X expr C Z 42 10 3 AND reg X expr expr Z 5C 4 1 MOV X...

Page 29: ...al category for one byte instructions are those that update the internal M8C registers This category holds the largest number of instructions ASL ASR CPL DEC INC MOV POP RET RETI RLC ROMX RRC SWAP The...

Page 30: ...code leaving room for a 16 bit destination address The second three byte instruction format shown in the sec ond row of Table 2 5 is used by the following two address ing modes Destination Direct Sour...

Page 31: ...arry flag bit is set or cleared in response to the result of several instructions It is also manipulated by the flag logic opcodes for example OR F 4 See the PSoC Designer Assembly Language User Guide...

Page 32: ...clearing the CPU_F PgMode bits Therefore the POINTER parameter is interpreted as an address in the page indicated by the MVI page pointers when the supervisory operation is called This allows the data...

Page 33: ...unction ends by setting the internal M8C reg isters CPU_SP CPU_PC CPU_X CPU_F CPU_A to 00h writing 00h to most SRAM addresses in SRAM Page 0 and then begins to execute user code at address 0000h See T...

Page 34: ...he flash No verifica tion of the data is performed but execution time is about 1 ms less than the WriteAndVerify function The WriteAnd Verify function is the recommended method for altering the data i...

Page 35: ...n the flash during manufacturing The flash for these tables is separate from the program flash and is not directly accessible It also returns a revision ID for the die do not confuse this with the sil...

Page 36: ...SRAM and flash Therefore the MVI write pointer MVW_PP and the MVI read pointer MVR_PP must be specified to the same SRAM page to control the page of RAM used for the operations Calibrate1 was created...

Page 37: ...o their POR state Then the SROM SWBootReset function executes followed by flash code execution beginning at address 0x0000 The HWBootReset function only requires that the CPU_A KEY1 and KEY2 be set up...

Page 38: ...register s PgMode bits and are covered in the sub sections after Basic Paging The function of the last two depend upon the CPU_F PgMode bits and are covered last 4 1 1 Basic Paging To increase the am...

Page 39: ...ions use data page pointers of their own MVR_PP and MVW_PP This allows a data buffer to be located away from other program variables but accessible without changing the Current Page Pointer CUR_PP An...

Page 40: ...shes the current value of the CPU_F register onto the stack and then clears the CPU_F register Thus by default any indexed memory access in an ISR is guaranteed to occur in SRAM Page 0 When the RETI i...

Page 41: ...isters refer to the Summary Table of the Core Registers on page 24 For additional information refer to the TMP_DRx register on page 219 4 2 2 CUR_PP Register The Current Page Pointer Register CUR_PP s...

Page 42: ...on Indexed address modes to operate on an SRAM page that is not equal to the current SRAM page However the effect this register has on indexed addressing modes is only enabled when the CPU_F 7 6 is se...

Page 43: ...MVI expr A instruction is executed in a device with more than one page of SRAM the SRAM address that is written by the instruction is determined by the value of the least significant bits in this regi...

Page 44: ...ice routine ISR executes tak ing 13 cycles During this time the following actions occur The PCH PCL and Flag register CPU_F are pushed onto the stack in that order The CPU_F register clears Because th...

Page 45: ...a posted interrupt from becoming pending It is especially important to understand the functionality of clearing posted interrupts if the configuration of the enCoRe V device is changed by the applicat...

Page 46: ...WINT bit in the INT_SW_EN register determines how an individual bit value written to an INT_CLR0 register is interpreted When ENSWINT is cleared the default state writing 1 s to the INT_CLR0 register...

Page 47: ...t for USB Endpoint1 Bit 4 Endpoint0 Read 0 no posted interrupt for USB Endpoint0 Read 1 posted interrupt present for USB Endpoint0 Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND...

Page 48: ...USB Endpoint8 Bit 3 Endpoint7 Read 0 no posted interrupt for USB Endpoint7 Read 1 posted interrupt present for USB Endpoint7 Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWI...

Page 49: ...allows GPIO interrupts to be enabled or masked Bit 3 Timer0 This bit allows Timer0 interrupts to be enabled or masked Bit 0 V Monitor This bit allows voltage monitor interrupts to be enabled or masked...

Page 50: ...is mask USB Endpoint6 interrupt 1 is unmask USB Endpoint6 interrupt Bit 1 Endpoint5 0 is mask USB Endpoint5 interrupt 1 is unmask USB Endpoint5 interrupt Bit 0 Endpoint4 0 is mask USB Endpoint4 inter...

Page 51: ...ister sim ply indicates that there are no pending interrupts The high est priority interrupt indicated by the value returned by a read of the INT_VC register is removed from the list of pending interr...

Page 52: ...163 6 1 Architectural Description The GPIO in the CY7C643xx and CY7C604xx devices are all uniform except that Port 0 and Port 1 GPIO have stronger high drive In addition to higher drive strength Port...

Page 53: ...ongly driven low by the system the enCoRe V is in However in the second line of code it cannot guarantee that only bit 7 is the one set to a strong 0 zero Because the AND instruction first reads the p...

Page 54: ...bal GPIO interrupt enable and the Global Interrupt Enable Setting the pin interrupt enable may immediately assert INTO if the Interrupt mode conditions are already being met at the pin After INTO pull...

Page 55: ...to the PRTxDR registers or to bypass the port s data register and output data from internal functions instead The bypass path is shown in Figure 6 1 by the Alt Data input which is selected by the Alt...

Page 56: ...the PRTxDR register returns the actual pin state as seen by the input buffer This may not be the same as the expected output state if the load pulls the pin more strongly than the pin s configured ou...

Page 57: ...rail If the 10b drive mode is used the pin is always read as a zero by the CPU and the pin cannot generate a useful interrupt It is not strictly required that you select High Z mode for analog operati...

Page 58: ...ices GPIO interrupts are controlled at each pin by the PRTxIE registers and also by the global GPIO bit in the INT_MSK0 register For additional information refer to the IO_CFG1 register on page 224 6...

Page 59: ...reference of all enCoRe V registers in address order refer to the Register Reference chapter on page 163 7 1 Architectural Description The ADC on enCoRe V devices is an independent block with a state...

Page 60: ...ction an external voltage can be connected to the input of the modulator for voltage conversion The ADC is run for a number of cycles set by the timer depending upon the resolution of the ADC desired...

Page 61: ...Bit 0 Reserved This bit is reserved and is 0 by default Analog Clock Configuration Register This is the configuration register for the analog clock in the Temperature Sensor ADC core Bits 7 to 4 ACLK...

Page 62: ...C_CNTL 7 0 Contains the MSB 8 bits of the ADC counter value Timer Period Low Byte Register This register holds the lower byte value of the timer period for the ADC operation Bits 7 to 0 Timer Period L...

Page 63: ...s inputs Bits 7 to 4 CMP_CR0 7 4 These 4 bits are reserved and are 0 by default Bits 3 to 0 Comparator Control These bits set the input to the comparator module For ADC operation this must be set to a...

Page 64: ...address and the data Section 7 4 of this chapter provides detailed information on the interface between the ADC and the application processor and how control and data transfer to and from the ADC is...

Page 65: ...DC Table 7 1 Status Code for ADC 7 4 3 ADC Usage Guidelines The temperature sensor block needs to be powered up by enabling the TS_EN before enabling the modulator This is required as this bit sets th...

Page 66: ...required clock speed with ACLK register TS_EN also controls the analog ground reference gener ation This bit is also required to be set for ADC only operation Select comparator inputs The default set...

Page 67: ...rmation The fre quency doubler circuit which produces SYSCLKX2 can be disabled to save power Registers for controlling these operations are found in the Digital Clocks chapter on page 96 8 2 Applicati...

Page 68: ...EraseAll Parameters 05h on page 35 has information on the location of various trim set tings stored in flash tables Firmware needs to read the right trim value for desired frequency and update the IM...

Page 69: ...en the bit is 1 the minimum amount of SRAM is initial ized after a watchdog reset For additional information refer to the CPU_SCR1 register on page 210 8 3 4 OSC_CR2 Register The Oscillator Control Re...

Page 70: ...scillator largely depends on the accuracy of the current reference input Prerequisite IP 8 7 Block Size Area 8 8 Gate Count 8 9 Block Pin List 8 10 Block Level Interfaces 8 11 Initialization 8 12 Woun...

Page 71: ...on Requirements Operating Condition Description Specification Units Min Max Table 8 6 DC IMO Specifications DC Param Description Block Specification Design Target Simulation Results BR4 Char Units Min...

Page 72: ...O is an oscillator with a nominal frequency of 32 kHz or 1 kHz It is used to generate sleep wakeup interrupts and watchdog resets This oscillator is also used as a clocking source for the digital bloc...

Page 73: ...his bit selects power down mode Set ting this bit high disables the oscillator and current bias when the ILO is powered down which results in slower startup time Setting this bit low keeps the small c...

Page 74: ...rocess of activating the ECO there must be a hold off period before using it as the 32 768 kHz source This hold off period is partially implemented in hardware using the sleep timer Firmware must set...

Page 75: ...O becomes the selected source at the end of the one second interval on the edge created by the sleep interrupt logic The one second interval gives the oscilla tor time to stabilize before it becomes t...

Page 76: ...e 5 power reduction 111 is the lowest gain setting This value is factory trimmed the typical value is 101 Bits 1 to 0 ECO_LP 1 0 These bits set the gain mode 00 is the highest power setting 11 is the...

Page 77: ...RTxIE Registers register on page 56 10 4 Usage Modes and Guidelines This block operates at extremely low current levels making it vulnerable to coupled noise Take care to avoid coupling noise from nei...

Page 78: ...page 163 11 1 Architectural Description Device components that are involved in Sleep and Watchdog operation are the selected 32 kHz clock the wakeup timer the Sleep bit in the CPU_SCR0 register the s...

Page 79: ...SLP_CFG2 register should be set before entering sleep state Deep Sleep Mode Configure the I2C_ON bit in the SLP_CFG2 register to 0 then USB Enable bit in the USB_CR0 regis ter to 0 and the X32ON bit...

Page 80: ...ion refer to the SLP_CFG3 Register on page 83 3 The maximum worst case duration of the wakeup sequence is 263 s based on the minimum specified ILO frequency of 19 kHz the minimum specified IMO frequen...

Page 81: ...em out of sleep state Individual interrupt enables as set in the interrupt mask registers are sufficient If the Global Interrupt Enable is not set the CPU does not service the ISR associated with that...

Page 82: ...e next Watchdog Reset WDR occurs anywhere from two to three times the current sleep interval setting If the sleep timer is near the beginning of its count the watchdog time out is closer to three time...

Page 83: ...s the device from deep sleep mode For additional information refer to the SLP_CFG2 register on page 236 11 3 4 SLP_CFG3 Register The Sleep Configuration Register SLP_CFG3 holds the configuration of th...

Page 84: ...p mode the supply voltage monitor circuit is active only during the buzz interval To properly detect and recover from a VDD brown out condition the configurable buzz rate must be frequent enough to ca...

Page 85: ...PU restarts There is no difference in wakeup from deep sleep or buzzed sleep because in all cases to achieve the power specifica tion the regulator references and core blocks must be shut 11 4 3 Bandg...

Page 86: ...hat registers the WDT terminal count is not reset by the WDR signal when it is asserted but is reset by all other resets This timing is shown in Figure 11 5 Figure 11 5 Watchdog Reset When enabled per...

Page 87: ...ss order refer to the Register Reference chapter on page 163 12 1 Architectural Description The Regulated I O is an NMOS replica bias voltage regulator This I O regulator has two operating ranges For...

Page 88: ...the comparator output voltage and the transistor threshold voltage This voltage is given as bias voltage to the gates of all pass tran sistors 12 1 4 Replica Structure The Replica Structure has a NMOS...

Page 89: ...to Port 1 pin 0 Otherwise it is mapped to Port 1 pin 3 Bit 1 REG_EN The Register Enable bit REG_EN con trols the regulator on Port 1 outputs Bit 0 IO INT This bit sets the GPIO Interrupt mode for all...

Page 90: ...r connected to the bus The analog global bus can be connected as a comparator input Figure 13 1 shows a block diagram of the I O analog mux system Figure 13 1 I O Analog Mux System For each pin the mu...

Page 91: ...ved bits with a value of 0 13 2 1 MUX_CRx Registers The Analog Mux Port Bit Enable Registers MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 and MUX_CR4 control the connection between the analog mux bus and the corre...

Page 92: ...2C Slave on page 103 System Resets on page 114 POR and LVD on page 121 SPI on page 123 Programmable Timer on page 137 Full Speed USB on page 141 Top Level System Resources Architecture The following f...

Page 93: ...8h I2C_DR Data 7 0 RW 00 SYSTEM RESET REGISTERS page 116 x FEh CPU_SCR1 IRESS SLIMO 1 0 IRAMDIS 0 x FFh CPU_SCR0 GIES WDRS PORS Sleep STOP XX POR REGISTERS page 121 1 E3h VLT_CR HPOR PORLEV 1 0 LVDTBE...

Page 94: ...r 7 0 R 00 0 32h USB_SOF1 Frame Number 10 8 R 0 0 33h USB_CR0 USB Enable Device Address 6 0 RW 00 0 34h USBIO_CR0 TEN TSE0 TD RD 00 0 35h USBIO_CR1 IOMode Drive Mode DPI DMI PSPUEN USB PUEN DPO DMO RW...

Page 95: ...h PMAx_RA Read Address 7 0 RW 00 1 41h PMAx_RA Read Address 7 0 RW 00 1 42h PMAx_RA Read Address 7 0 RW 00 1 43h PMAx_RA Read Address 7 0 RW 00 1 4Ch PMAx_RA Read Address 7 0 RW 00 1 4Dh PMAx_RA Read...

Page 96: ...llator is selected all device functions are clocked from a derivative of SYSCLK or are resynchronized to SYSCLK All external asynchronous signals and the internal low speed oscillator are resynchroniz...

Page 97: ...o do this will cause the device to hang up An example implementation is shown here OSC_CR2 0x04 Disconnect External Clock and connect IMO to SYSCLK M8C_Sleep Entering sleep asm nop OSC_CR2 0x04 Connec...

Page 98: ...al Clock with a CPU Clock Divider of Two or Greater Figure 14 3 Switch from IMO to External Clock with the CPU Running with a CPU Clock Divider of One CPUCLK IMO Extenal Clock SYSCLK IOW_ EXTCLK bit I...

Page 99: ...a USB part A 0 runs the IMO with sacrificed DNL by consuming less power A 1 runs the IMO with better DNL by consuming more power Bit 0 USB_CLK_ON This bit either enables or disables the clocks to the...

Page 100: ...TRM Document No 001 32519 Rev H 100 Digital Clocks Bit 0 P10ENBit enables pin P1 0 to output the sleep inter rupt SLPINT 0 No internal signal output to P1 0 1 Output SLPINT to P1 0 For additional inf...

Page 101: ...speed circuit therefore the default CPU speed is 6 0 MHz See External Clock on page 97 for more information on the supported frequencies for externally supplied clocks The CPU frequency is changed wi...

Page 102: ...LKEN bit is set the external clock becomes the source for the internal clock tree SYSCLK which drives most device clocking functions All external and internal sig nals including the low speed oscillat...

Page 103: ...ace the enCoRe V device to a two wire I2C serial communications bus To eliminate the need for excessive M8C microcontroller intervention and overhead the block provides I2C specific support for status...

Page 104: ...slave address there is also a 10 bit address mode and a read write RW bit The RW bit sets the direction of data transfer The addressed slave is required to acknowledge ACK the bus by pulling the data...

Page 105: ...o respond to the events and conditions on the bus Figure 15 4 is a graphical representation of a typical data transfer from the slave perspective Figure 15 4 Slave Operation 1 7 8 1 7 8 9 STAR T 7 Bit...

Page 106: ...tically ACKed and upon a mismatch the address is automatically NAKed and the hardware reverts to an idle state waiting for the next Start detection You must configure the compare address in the I2C_AD...

Page 107: ...y firmware Bits 3 and 2 Clock Rate 1 0 These bits offer a selection of three sampling and bit rates All block clocking is based on the SYSCLK input which is nominally12 MHz or 6 MHz The sampling rate...

Page 108: ...gister on page 193 Table 15 2 Enable Operation in I2C_CFG Enable Block Operation No Disabled The block is disconnected from the GPIO pins P1 5 and P1 7 The pins may be used as general purpose I O When...

Page 109: ...t by the firmware This bit may only be cleared if the Byte Complete status bit is set If the Stop Interrupt Enable bit is set an interrupt is also generated upon Stop detection It is never automatical...

Page 110: ...depends upon the current operating mode 0 ACK The master wants to read another byte The slave loads the next byte into the I2C_DR Register and sets the Transmit bit in the I2C_SCR register to continue...

Page 111: ...the I2C_CFG Register If any of the three divider taps is selected that clock is resynchronized to SYSCLK The resulting clock is routed to all of the synchronous elements in the design Figure 15 5 I2C...

Page 112: ...a transmitted byte Figure 15 7 Byte Complete Address LRB Timing Figure 15 8 shows the timing for Stop status This bit is set and the interrupt occurs two clocks after the synchronized and filtered SD...

Page 113: ...pt occurs two clocks after the rising edge of SCL_IN see Status Timing on page 112 As illustrated in Figure 15 10 firmware has until one clock after the falling edge of SCL_IN to write to the I2C_SCR...

Page 114: ...e on parts that contain an XRES pin Watchdog Reset WDR This optional reset occurs when the watchdog timer expires before being cleared by user firmware Watchdog resets default to off Internal Reset IR...

Page 115: ...nly after the core has powered up a delay of about 1 ms 16 2 3 GPIO Behavior on External Reset During external reset XRES 1 both P1 0 and P1 1 drive resistive low 0 After XRES deasserts these pins con...

Page 116: ...ion There is no need for concern when this bit is set It is pro vided for systems that may be sensitive to boot time so that they can determine if the normal one pass boot time was exceeded For more i...

Page 117: ...a POR or XRES Bit 3 Sleep This bit is used to enter Low power Sleep mode when set To wake up the system this register bit is cleared asynchronously by any enabled interrupt Two spe cial features of th...

Page 118: ...assed and the core powered with a higher voltage than specified For this reason avoid shifting key AC52h while in reset During XRES XRES 1 the IMO is powered off for low power during startup After XRE...

Page 119: ...1 N 512 Follows POR XRES IMO PD IMO not to scale CPU Reset PPOR with no IPOR Reset while PPOR is high and to the end of the next 32K cycle IMO off 1 cycle IMO on before the CPU reset is released Note...

Page 120: ...owered up The IMO is always on for at least one CLK32K cycle before CPU reset is deasserted Table 16 1 Reset Functionality Item IPOR Part of POR PPOR Part of POR XRES WDR Reset Length While POR 1 Whil...

Page 121: ...nce chapter on page 163 17 1 Architectural Description The power on reset POR and low voltage detect LVD circuits provide protection against low voltage conditions The POR function senses Vcc and Vcor...

Page 122: ...1 0 These bits along with HPOR sets one of the four values for the PPOR trip voltage See Table 21 1 on page 231 See the DC POR and LVD Specifications table in the Elec trical Specifications section of...

Page 123: ...the basic signals in a simple connection Figure 18 2 Basic SPI Configuration A device can be a master or slave A master outputs clock and data to the slave device and inputs slave data A slave device...

Page 124: ...rwise no subsequent interrupts are generated 18 1 3 SPI Slave Function The SPI Slave SPIS offers SPI operating modes 0 3 By default the MSb of the data byte is shifted out first An addi tional option...

Page 125: ...nization can be bypassed by setting the BYPS bit in the SPI_CFG register 18 2 Register Definitions The following registers are associated with the SPI and are listed in address order The register desc...

Page 126: ...e data from this register is loaded into the Shift register on the following clock edge and a transmission is initiated If a transmission is currently in progress this register serves as a buffer for...

Page 127: ...k For additional information refer to the SPI_CR register on page 168 18 2 3 1 SPI Control Register Definitions Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0 2Bh SPI_CR LSb Fir...

Page 128: ...Bit 1 Int Sel Interrupt Select This bit selects which condi tion produces an interrupt Bit 0 Slave This bit determines whether the block func tions as a master or slave For additional information ref...

Page 129: ...he clock and the next data is output on the trailing edge of the clock When the clock phase is 1 it means that the next data is output on the leading edge of the clock and that data is registered as a...

Page 130: ...block is disabled all internal state is held in a reset state When the Enable bit in the SPI_CR register is set the reset is synchronously released and the clock generation is enabled All eight taps f...

Page 131: ...available with one half clock setup time to the next clock a new byte trans mission is initiated An SPIM block receives a byte at the same time that it sends one The SPI Complete or RX Reg Full can be...

Page 132: ...tional interrupt and is generated when eight bits of data and clock are sent In modes 0 and 1 this occurs one half cycle after RX Reg Full is set because in these modes data is latched on the leading...

Page 133: ...Transfer in Progress SCLK Mode 1 SCLK Mode 0 SS Transfer in Progress Transfer in Progress MODE 2 3 Phase 1 Output on leading edge Input on trailing edge SCLK Polarity 0 Mode 2 MOSI MISO SCLK Polarity...

Page 134: ...ock is disabled the MISO output reverts to its idle 1 state All internal state is reset including CR0 status to its configuration specific reset state except for DR0 DR1 and DR2 which are unaffected N...

Page 135: ...un The timing of these status bits are identical to the SPIM with the exception of TX Reg Empty which is covered in the section on TX data queuing Status Clear On Read Refer to the same subsection in...

Page 136: ...one half clock minimum before the leading edge with a knowledge of system latencies and response times Figure 18 11 Mode 0 and 1 Transfer in Progress Figure 18 12 illustrates TX data loading in modes...

Page 137: ...START bit in the configuration register is cleared after completion of one full count cycle Setting the START bit restarts the timer Figure 19 1 Programmable Timer Block Diagram 19 1 1 Operation When...

Page 138: ...Figure 19 2 Continuous Operation Example Figure 19 3 One Shot Operation Example PTDATA1 PTDATA0 Clock Start One Shot 00h 00h 03h 02h 01h 00h 03h 02h 01h 00h 03h 02h 01h Count TC 0003h IRQ TC Period T...

Page 139: ...0 START This bit starts the timer counting from a full count The full count is determined by the value loaded into the data registers This bit is cleared when the timer is run ning in one shot mode up...

Page 140: ...TA0 Register The Programmable Timer Data Register 0 PT0_DATA0 PT1_DATA0 PT2_DATA0 holds the lower 8 bits of the pro grammable timer s count value Bits 7 to 0 DATA 7 0 This is the lower byte of a 16 bi...

Page 141: ...configurable as either IN or OUT 20 2 Application Description The individual components and issues of the USB system are described in detail in the following sections 20 2 1 USB SIE The USB Serial Int...

Page 142: ...01 Accept NAK NAK NAK IN and OUT token Status OUT Only 0010 Accept STALL Check For control endpoint STALL IN and ACK zero byte OUT STALL IN OUT 0011 Accept STALL STALL For control endpoint STALL IN an...

Page 143: ...e a channel where the endpoint is inactive 2 Write the channel s PMAx_WA register with the first address in SRAM that must be used by this channel 3 Write data to the channel s PMAx_DR register The PM...

Page 144: ...unt reported in the endpoint count registers includes the ignored bytes 20 2 3 Oscillator Lock The enCoRe V device can operate without using any exter nal components such as a crystal and still achiev...

Page 145: ...gisters PMAx_DR endpoint count registers EPx_CNTx endpoint 0 data register EP0_DRx and start of frame registers USB_SOFx These registers are reset after the device comes out of sleep An alternative is...

Page 146: ...e V LV CY7C604xx TRM Document No 001 32519 Rev H 146 Full Speed USB Figure 20 2 Transceiver and Regulator Block Diagram VOLTAGE REGULATOR 5V 3 3V S1 1 5K 5K PS2 Pull Up DP DM TEN TD PDN RD DPO RSE0 DM...

Page 147: ...0 USB_CR0 is used to set the enCoRe V s USB address and enable the USB system resource The USB_MISC_CR register on page 220 must be set correctly for the bits in this register to function as described...

Page 148: ...t 1 is drive mode DMI and DPI determine state of the D and D pins Bit 6 Drive Mode If the IOMode bit is set this bit config ures the D and D pins for either CMOS drive or open drain drive If IOMode is...

Page 149: ...set to 1 the CPU cannot write to the EP0_DRx registers This prevents firmware from overwriting an incoming setup transaction before firmware has a chance to read the setup data This bit is cleared by...

Page 150: ...d values are 0 to 8 For OUT or setup transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes Valid values are 2 to 10 For additional information r...

Page 151: ...cket and the two byte CRC are written to the USB s dedicated SRAM If the number of data bytes received is exactly the same as the 9 bit count then only the data is updated into the USB SRAM and the CR...

Page 152: ...does not update for some end point mode settings 0 is error in data received 1 is no error Bit 0 Count MSB This bit is the one MSb of a 9 bit coun ter The LSb are the Data Count 7 0 bits of the EPx_C...

Page 153: ...ransaction bit is set whenever the SIE engages in a transaction to the regis ter s endpoint that completes with an ACK packet This bit is cleared by any writes to the register 0 is no ACKed trans acti...

Page 154: ...n the M8C case this register always returns the next SRAM address that is used by the PMA channel if a byte is written to the channel s data register PMAx_DR by the M8C For additional information refe...

Page 155: ...for the next read from the chan nel s PMAx_DR register When the USB SIE reads the PMAx_DR register it also receives a pre loaded value which triggers the PMA logic to fetch the next value in SRAM to b...

Page 156: ...by the USB SIE or by the M8C In the USB SIE case this register always returns the beginning SRAM address for the PMA channel In the M8C case this register always returns the next SRAM address that is...

Page 157: ...2 USB_SE_EN The single ended outputs of USBIO is enabled or disabled based upon this bit setting Set this bit to 1 when using this part as a USB part for USB transac tions to occur Set this bit to 0 t...

Page 158: ...nternal Main Oscillator IMO chapter on page 67 or refer to the IMO_TR1 register on page 238 in the Register Details chapter Bits 2 to 0 Fine Trim 2 0 These bits provide a fine tuning capability to the...

Page 159: ...referred to as I O space and is broken into two parts Bank 0 user space and Bank 1 configuration space The XIO bit in the Flag regis ter CPU_F determines which bank the user is currently in When the X...

Page 160: ...NT_CLR0 DA RW 196 1B PMA_DR 5B RW 179 9B INT_CLR1 DB RW 198 1C PMA4_DR 5C RW 179 9C INT_CLR2 DC RW 200 1D PMA5_DR 5D RW 179 9D DD 1E PMA6_DR 5E RW 179 9E INT_MSK2 DE RW 202 1F PMA7_DR 5F RW 179 9F INT...

Page 161: ...RA 52 RW 217 92 ECO_ENBUS D2 RW 221 13 PMA15_RA 53 RW 217 93 ECO_TRIM D3 RW 222 14 EP1_CR0 54 218 94 D4 15 EP2_CR0 55 218 95 D5 16 EP3_CR0 56 218 96 D6 17 EP4_CR0 57 218 97 D7 18 EP5_CR0 58 218 98 MUX...

Page 162: ...A 39 RW 216 79 B9 F9 PMA6_WA 3A RW 216 7A BA IMO_TR1 FA RW 238 PMA7_WA 3B RW 216 7B BB FB PMA0_RA 3C RW 217 7C BC FC PMA1_RA 3D RW 217 7D USB_MISC_CR BD RW 220 FD PMA2_RA 3E RW 217 7E BE FE PMA3_RA 3F...

Page 163: ...additional register information 4 Detailed register bit descriptions Use the register tables in addition to the detailed register bit descriptions to determine which bits are reserved Reserved bits ar...

Page 164: ...0 but is accessed in both Bank 0 and Bank 1 21 3 1 PRTxDR Port Data Registers These registers allow write or read access or the current logical equivalent of pin voltage The upper nibble of the PRT4DR...

Page 165: ...the Register Definitions on page 56 in the GPIO chapter 7 0 Interrupt Enables 7 0 These bits enable the corresponding port pin interrupt Only four LSB are used because this port has four pins 0 Port...

Page 166: ...ister This register is the SPI s transmit data register For additional information refer to the Register Definitions on page 125 in the SPI chapter 7 0 Data 7 0 Data for selected function Individual R...

Page 167: ...ister This register is the SPI s receive data register For additional information refer to the Register Definitions on page 125 in the SPI chapter 7 0 Data 7 0 Data for selected function Individual Re...

Page 168: ...Optional interrupt 4 TX Reg Empty Reset state and the state when the block is disabled is 1 0 Indicates that a byte is currently buffered in the TX register 1 Indicates that a byte is written to the T...

Page 169: ...a USB Start of Frame register 0 For additional information refer to the Register Definitions on page 147 in the Full Speed USB chapter 7 0 Frame Number 7 0 Contains the lower eight bits of the frame n...

Page 170: ...e cells and are not described in the bit description section Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 147 in the Full...

Page 171: ...as described here For additional information refer to the Register Definitions on page 147 in the Full Speed USB chapter 7 USB Enable This bit enables the enCoRe V device to respond to USB traffic 0 U...

Page 172: ...s bit must be cleared to allow the internal SIE to drive the pins The most common reason for manually transmitting is to force a resume state on the bus 0 Manual transmission off 1 Manual transmission...

Page 173: ...as no effect if IOMode 0 0 D pin drives a logic level LOW 1 If Drive Mode bit is 0 D pin is tri stated If Drive Mode bit is 1 D pin drives a logic level HIGH 4 DMI This bit drives the D pin This bit h...

Page 174: ...his bit indicates a valid IN packet was received 5 OUT Received When set this bit indicates an OUT packet was received 4 ACKed Transaction When set this bit indicates a valid OUT packet has been recei...

Page 175: ...ritten with a value of 0 For additional information refer to the Register Definitions on page 147 in the Full Speed USB chapter 7 Data Toggle This bit selects the data packet s toggle state 6 Data Val...

Page 176: ...ation refer to the Register Definitions on page 147 in the Full Speed USB chapter 7 0 Data Byte 7 0 These registers are shared for both transmit and receive Individual Register Names and Addresses 0 3...

Page 177: ...tional information refer to the Register Definitions on page 147 in the Full Speed USB chapter 7 Data Toggle This bit selects the data packet s toggle state 6 Data Valid This bit is used for OUT trans...

Page 178: ...ter Definitions on page 147 in the Full Speed USB chapter 7 0 Data Count 7 0 These bits are the eight LSb of a 9 bit counter The MSb is the Count MSb of the EPx_CNT0 register Individual Register Names...

Page 179: ...Byte 7 0 When the M8C writes to this register the PMA registers the byte and then stores the value at the address in SRAM indicated by the PMAx_WA register Individual Register Names and Addresses 0 5...

Page 180: ...rved 10b P0 1 pin 11b P0 3 pin 5 4 INN1 1 0 Comparator 1 Negative Input Select 00b VREF 1 0 V 01b Ref Lo approximately 0 6 V 10b Ref Hi approximately 1 2 V 11b Reserved 3 2 INP0 1 0 Comparator 0 Posit...

Page 181: ...k If the bit is set to 1 the timer runs on the CPU clock otherwise the timer runs on the 32 kHz clock 1 One Shot 0 Continuous count mode Timer reloads the count value from the data registers upon each...

Page 182: ...value for the device For additional information refer to the Register Definitions on page 139 in the Programmable Timer chapter 7 0 DATA 7 0 This is the upper byte of a 16 bit timer The lower byte is...

Page 183: ...its of the count value For additional information refer to the Register Definitions on page 139 in the Programmable Timer chapter 7 0 DATA 7 0 This is the lower byte of a 16 bit timer The upper byte i...

Page 184: ...ck If the bit is set to 1 the timer runs on the CPU clock otherwise the timer runs on the 32 kHz clock 1 One Shot 0 Continuos count mode Timer reloads the count value from the data registers upon each...

Page 185: ...k If the bit is set to 1 the timer runs on the CPU clock otherwise the timer runs on the 32 kHz clock 1 One Shot 0 Continuous count mode Timer reloads the count value from the data registers upon each...

Page 186: ...n this bit is set to a 1 hardware address compare is enabled When enabled bit 3 in the I2C_SCR register is not set Upon a compare the address is automatically ACKed and upon a mis match the address is...

Page 187: ...In the table note that the reserved bit is a grayed table cell and not described in the bit description section Always write reserved bits with a value of 0 For additional information refer to the Reg...

Page 188: ...e bit description section Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 41 in the RAM Paging chapter 2 0 Page Bits 2 0 Bit...

Page 189: ...the bit description section Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 41 in the RAM Paging chapter 2 0 Page Bits 2 0 B...

Page 190: ...description section Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 41 in the RAM Paging chapter 2 0 Page Bits 2 0 Bits det...

Page 191: ...le cells and are not described in the bit description section Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 41 in the RAM...

Page 192: ...ble cells and are not described in the bit description section Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 41 in the RAM...

Page 193: ...n page 106 in the I2C Slave chapter 6 P Select I2C Pin Select 0 P1 5 and P1 7 1 P1 0 and P1 1 Note Read the I2 C Slave chapter on page 103 for a discussion of the side effects of choosing the P1 0 and...

Page 194: ...received byte 3 Address 0 Status bit It must be cleared by firmware with a write of 0 to the bit position 1 The received byte is a slave address 2 Transmit Bit is set by firmware to define the directi...

Page 195: ...ister This register is read only for received data and write only for transmitted data For additional information refer to the Register Definitions on page 106 in the I2C Slave chapter 7 0 Data 7 0 Re...

Page 196: ...ct Write 1 AND ENSWINT 1 Post an interrupt for I2C 6 Sleep Read 0 No posted interrupt for sleep timer Read 1 Posted interrupt present for sleep timer Write 0 AND ENSWINT 0 Clear posted interrupt if it...

Page 197: ...if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt for Timer 0 V Monitor Read 0 No posted interrupt for Supply Voltage Monitor Read 1...

Page 198: ...t present for USB Endpoint3 Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt for USB En...

Page 199: ...1 Post an interrupt for USB Start of Frame SOF 2 USB_BUS_RST Read 0 No posted interrupt for USB Bus Reset Read 1 Posted interrupt present for USB Bus Reset Write 0 AND ENSWINT 0 Clear posted interrupt...

Page 200: ...NT is set an interrupt is posted in the interrupt controller For additional information refer to the Register Definitions on page 46 in the Interrupt Controller chapter 5 USB_WAKE Read 0 No posted int...

Page 201: ...ar posted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt for USB Endpoint6 1 Endpoint5 Read 0 No posted interrupt for US...

Page 202: ...f 0 For additional information refer to the Register Definitions on page 46 in the Interrupt Controller chapter 5 USB Wakeup 0 Mask USB Wakeup interrupt 1 Unmask USB Wakeup interrupt 4 Endpoint8 0 Mas...

Page 203: ...t 1 Unmask USB Endpoint3 interrupt 6 Endpoint2 0 Mask USB Endpoint2 interrupt 1 Unmask USB Endpoint2 interrupt 5 Endpoint1 0 Mask USB Endpoint1 interrupt 1 Unmask USB Endpoint1 interrupt 4 Endpoint0 0...

Page 204: ...er to the Register Definitions on page 46 in the Interrupt Controller chapter 7 I2C 0 Mask I2C interrupt 1 Unmask I2C interrupt 6 Sleep 0 Mask Sleep interrupt 1 Unmask Sleep interrupt 5 SPI 0 Mask SPI...

Page 205: ...ed table cells and are not described in the bit description section Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 46 in th...

Page 206: ...errupts when written For additional information refer to the Register Definitions on page 46 in the Interrupt Controller chapter 7 0 Pending Interrupt 7 0 Read Returns vector for highest priority pend...

Page 207: ...e watchdog timer and the sleep timer together For additional information refer to the Register Definitions on page 82 in the Sleep and Watchdog chapter 7 0 WDSL_Clear 7 0 Any write clears the watchdog...

Page 208: ...ddress mode instructions are referred to Page 0 Indexed Address mode instructions are referred to the RAM page specified by the stack page pointer STK_PP 10b Direct Address mode instructions are refer...

Page 209: ...v H 209 x F7h 21 3 42 CPU_F continued 1 Zero Set by the M8C CPU Core to indicate whether there was a zero result in the previous logical arithme tic operation 0 Not equal to zero 1 Equal to zero 0 GIE...

Page 210: ...ions on page 116 in the Sys tem Resets chapter 7 IRESS This bit is read only 0 Boot phase only executed once 1 Boot phase occurred multiple times 4 3 SLIMO 1 0 These bits set the frequency range for t...

Page 211: ...y for GIES Its use is discouraged as the Flag register is now readable at address x F7h read only 5 WDRS Watchdog Reset Status This bit may not be set by user code however it may be cleared by writing...

Page 212: ...he two registers are treated as a group These are referred to as DM1 and DM0 or together as DM 1 0 All drive mode bits are shown in the sub table 10 refers to the combination in order of bits in a giv...

Page 213: ...e mode bits are shown in the sub table 10 refers to the combination in order of bits in a given bit position however this register only controls the most significant bit MSb of the drive mode The uppe...

Page 214: ...ss Bypass Synchronization 0 All pin inputs are doubled and synchronized 1 Input synchronization is bypassed 3 SS_ Slave Select in Slave mode 0 Slave selected 1 Slave not selected 2 SS_EN_ Internal Sla...

Page 215: ...bus This bit is only set by the hardware Writing a 0 clears this bit Writing a 1 preserves its present state 0 No activity 1 Non idle activity D Low was detected since the last time the bit was clear...

Page 216: ...er 7 0 Write Address 7 0 The value returned when this register is read depends on whether the PMA channel is being used by the USB SIE or by the M8C Individual Register Names and Addresses 1 34h PMA0_...

Page 217: ...n this register is read depends on whether the PMA channel is being used by the USB SIE or by the M8C In the USB case this register always returns the beginning SRAM address for the PMA channel Indivi...

Page 218: ...Mode bits are set to ACK IN This bit must be clear for all other modes 5 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK 4 ACKed Tx...

Page 219: ...s All bits in this register are reserved for enCoRe V devices with 256 bytes of SRAM For additional information refer to the Register Definitions on page 41 in the RAM Paging chapter 7 0 Data 7 0 Gene...

Page 220: ...is register setting When this bit is 0 default regardless of the DP and DM state the DPO and DMO bits of USBIO_CR1 are 11b 1 USB_ON This bit is used by the IMO DAC block to either work with better DNL...

Page 221: ...escription section Reserved bits should always be written with a value of 0 See the Application Overview on page 75 for the proper sequence for enabling the ECO 2 0 ECO_ENBUS 2 0 These bits should be...

Page 222: ...page 91 in the I O Analog Multiplexer chapter 4 2 ECO_XGM 2 0 These bits set the amplifier gain The high power mode ECO_LPM 0 step size of the current source is approximately 400 nA In low power mode...

Page 223: ...the Register Definitions on page 91 in the I O Analog Multiplexer chapter 7 0 ENABLE 7 0 Each bit controls the connection between the analog mux bus and the corresponding port pin For example MUX_CR2...

Page 224: ...no compatibility issues when Port 1 is communicating at regulated voltage levels 0 Standard threshold of VIH VIL 1 Reduce threshold of VIH VIL 2 SPICLK_ON_P10 When set to 1 the SPI clock is mapped to...

Page 225: ...en with a value of 0 For additional information refer to the Register Definitions on page 99 in the Digital Clocks chapter 7 P16D Bit selects the data output to P1 6 when P16EN is high 0 Select Timer...

Page 226: ...x enCoRe V LV CY7C604xx TRM Document No 001 32519 Rev H 226 1 DDh 21 4 14 OUT_P1 continued 0 P10EN Bit enables pin P1 0 to output the sleep interrupt SLPINT 0 No internal signal output to P1 0 1 Outpu...

Page 227: ...EG_LEVEL 2 0 These bits select output regulated supply 1 0 REG_CLOCK 1 0 The Regulated I O charge pump can operate with a maximum clock speed of 12 MHZ The REG_CLOCK 1 0 bits select clocking options f...

Page 228: ...o stay powered during sleep 0 Buzz bandgap during power down 1 Bandgap is always powered even during sleep 4 3 Sleep 1 0 Sleep interval For 32 kHz ILO For 1 kHz ILO 00b 1 95 ms 512 Hz 64 ms 15 6 Hz 01...

Page 229: ...that indicates that the ECO_EX bit was previously written to When this bit is a 1 this indicates that the ECO_CONFIG register was written to and is now locked When this bit is a 0 the register was no...

Page 230: ...0 For additional information refer to the Register Definitions on page 99 in the Digital Clocks chapter 4 CLK48MEN This is the 48 MHz clock enable bit 0 Disables the 48 MHz clock 1 Enables the 48 MHz...

Page 231: ...ion of the enCoRe V device datasheet for voltage tolerances for each setting 5 4 PORLEV 1 0 These bits along with HPOR sets one of the four values for the PPOR trip voltage See Table 21 1 3 LVDTBEN En...

Page 232: ...d table cells and are not described in the bit description section Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 122 in th...

Page 233: ...le Read operation The new value must be written at the lower frequency range That is when moving to a higher frequency range change the IMO_TR value and then change the range SLIMO 1 0 in CPU_SCR1 Whe...

Page 234: ...ved bits with a value of 0 For additional information refer to the Register Definitions on page 73 in the Internal Low speed Oscillator chapter 6 PD_MODE This bit selects power down mode Setting this...

Page 235: ...formation refer to the Register Definitions on page 82 in the Sleep and Watchdog chapter 7 6 PSSDC 1 0 Sleep Duty Cycle Controls the ratios in numbers of 32 768 kHz clock periods of on time versus off...

Page 236: ...ol additional selections for POR LVD buzz rates 00 Compatibility mode buzz rate is determined by PSSDC bits 01 Duty cycle is 1 32768 10 Duty cycle is 1 8192 11 Reserved 1 I2C_ON This bit enables the s...

Page 237: ...doubled for the wakeup sequence 5 4 T2TAP 1 0 These bits control the duration of the T2 T4 sequence see Figure 11 2 on page 80 by selecting a tap from the WakeupTimer Note The T2 delay is only valid...

Page 238: ...bit description section Reserved bits should always be written with a value of 0 For additional information refer to the Register Definitions on page 68 in the Inter nal Main Oscillator chapter 7 0 F...

Page 239: ...rmation is stored algorithm A procedure for solving a mathematical problem in a finite number of steps that frequently involve repetition of an operation ambient temperature The temperature of the air...

Page 240: ...e design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE to produce a zero temperature coefficient ideally reference bandwidth 1 The frequency...

Page 241: ...tate make buffer 1 A storage area for data that is used to compensate for a speed difference when transferring data from one device to another Usually refers to an area reserved for I O operations int...

Page 242: ...s a pre deter mined value crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal Typically a piezoelec tric crystal is less sensitive to ambient temperature t...

Page 243: ...by means of addresses that indicate the physi cal location of the data duty cycle The relationship of a clock period high time to its low time expressed as a percent E emulator Duplicates provides an...

Page 244: ...ting paths between an electric circuit or equipment and the earth or some con ducting body serving in place of the earth H hardware A comprehensive term for all of the physical parts of a computer or...

Page 245: ...uit input A point that accepts data in a device process or channel input output I O A device that introduces data into or extracts data from a system instruction An expression that specifies one opera...

Page 246: ...t of time the signal has a value of 0 in one period for a periodic digital signal low voltage detect LVD A circuit that senses Vdd and provides an interrupt to the system when Vdd falls below a select...

Page 247: ...example the digital block may be in either counter mode or timer mode modulation A range of techniques for encoding information on a carrier signal typically a sine wave signal A device that performs...

Page 248: ...ical signal through a circuit pending interrupts An interrupt that is triggered but is not serviced either because the processor is busy servicing another interrupt or global interrupts are disabled p...

Page 249: ...r A storage device with a specific capacity such as a bit or byte reset A means of bringing a system back to a known state See hardware reset and software reset resistance The resistance to the flow o...

Page 250: ...es between the cascaded devices and an external interface The controlling device is called the master device software A set of computer programs procedures and associated documentation concerned with...

Page 251: ...he transistor is a solid state semiconductor device used for amplification and switching and has three terminals A small current or voltage applied to one terminal controls the current through the oth...

Page 252: ...eed to stay the same value or level when not in scope Vss A name for a power net meaning voltage source The most negative power supply signal W watchdog timer A timer that must be serviced periodicall...

Page 253: ...68 Clock Rate bits 193 Clock Sel bit 214 clock external digital 97 switch operation 97 clocks digital See digital clocks CMP_MUX register 180 comparator in regulated IO 88 configuration register in SP...

Page 254: ...etting development kits 12 support 12 upgrades 12 I I2C bit in INT_CLR0 register 196 in INT_MSK0 register 204 I2C slave 103 application overview 105 architecture 103 basic data transfer 104 basic IO t...

Page 255: ...2 P P10EN bit 226 P12EN bit 225 P16D bit 225 P16EN bit 225 Page bits in CUR_PP register 188 in IDX_PP register 190 in MVR_PP register 191 in MVW_PP register 192 in STK_PP register 189 pass transistors...

Page 256: ...207 RX Reg Full bit 168 S serial peripheral interconnect See SPI Slave bit 214 slave function for SPI 124 slave operation I2C 105 sleep and watchdog 78 application overview 81 architecture 78 bandgap...

Page 257: ...m resources architecture 92 overview 10 92 register summary 93 T TableRead function in SROM 35 technical support 12 Timer1 0 bits in INT_CLR0 register 197 in INT_MSK0 register 204 timing diagrams I2C...

Reviews:

No comments

Related manuals for enCoRe V CY7C643 Series

Brand: EEPD Pages: 111

Brands by name

0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Popular brands

Load more brands