Cypress enCoRe V CY7C643 Series Technical Reference Manual Download Page 101

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enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H

101

Digital Clocks

14.2.3

OSC_CR0 Register

The Oscillator Control Register 0 (OSC_CR0) configures
various features of internal clock sources and clock nets.

Bit 7: X32ON.

This bit enables the 32-kHz external crystal

oscillator (ECO) when set high. See the

Application Over-

view on page 75

for the proper sequence to enable the

ECO.

Bit 6: Disable Buzz.

Setting this bit high causes the band-

gap and POR/LVD systems to remain powered off continu-
ously during sleep. In this case, there is no periodic “buzz”
(brief wakeup) of these functions during sleep. This bit has
no effect when the No Buzz bit is set high.

Bit 5: No Buzz.

Normally, when the SLEEP bit is set in the

CPU_SCR register, all enCoRe V device systems are pow-
ered  down,  including  the  bandgap  reference.  However,  to
facilitate  the  detection  of  POR  and  LVD  events  at  a  rate
higher  than  the  sleep  interval,  the  bandgap  circuit  is  pow-
ered up periodically (for about 60



s) at the Sleep System

Duty Cycle, which is independent of the sleep interval and
typically higher. When the No Buzz bit is set, the Sleep Sys-
tem Duty Cycle value is overwritten and the bandgap circuit
is forced to be on during sleep. This results in faster
response to an LVD or POR event (continuous detection as
opposed to periodic), at the expense of higher average
sleep current.

Bits 4 and 3: Sleep[1:0].

The available sleep interval

selections are shown in the following table. Sleep intervals
are approximate based upon the accuracy of the internal
low-speed oscillator.

Bits 2 to 0: CPU Speed[2:0].

The enCoRe V M8C oper-

ates over a range of CPU clock speeds, allowing you to tai-
lor the M8C’s performance and power requirements to the
application.

The reset value for the CPU speed bits is 010b. Therefore,
the default CPU speed is one-half of the clock source. The
internal main oscillator is the default clock source for the
CPU speed circuit; therefore, the default CPU speed is 6.0
MHz. See

External Clock on page 97

for more information

on the supported frequencies for externally supplied clocks.

The  CPU  frequency  is  changed  with  a  write  to  the
OSC_CR0  register.  There  are  eight  frequencies  generated
from a power-of-two divide circuit that is selected by a 3-bit
code. At any given time, the CPU 8-to-1 clock mux is select-
ing  one  of  the  available  frequencies,  which  is  resynchro-
nized  to  the  24-MHz  master  clock  at  the  output.  The  IMO
frequency  is  also  selectable,  as  discussed  in

Architectural

Description on page 67

. This offers an option to lower both

system and CPU clock speed to save power. The selections
are shown in the following table (reset state is 010b).

An automatic protection mechanism is available for systems
that need to run at peak CPU clock speed but cannot guar-
antee a high enough supply voltage for that clock speed.
See the LVDTBEN bit in the

VLT_CMP Register on

page 122

for more information.

Note

During USB operation, the CPU speed can be set to

any setting. Be aware that USB throughput decreases with a
decrease in CPU speed. For maximum throughput, the CPU
clock should be made equal to the system clock. The sys-
tem clock must be 24 MHz for USB operation.

For additional information, refer to the

OSC_CR0 on page

228

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1