enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
228
1,E0h
21.4.16 OSC_CR0
Oscillator Control Register 0
This register is used to configure various features of internal clock sources and clock nets.
In the table, note that the reserved bit is a grayed table cell and is not described in the bit description section. Reserved bits
must always be written with a value of ‘0’. For additional information, refer to the
Register Definitions on page 99
in the Digital
Clocks chapter.
7
X32ON
Select bit for the external 32-kHz external crystal oscillator (ECO). See the
for the proper sequence for enabling the ECO.
0
The internal 32 kHz oscillator is the source of the 32K clock.
1
The external crystal oscillator is the source of the 32K clock.
6
Disable Buzz
Option to disable buzz during sleep. This bit has lower priority than the No Buzz bit. Therefore, if No
Buzz = 1, the Disable Buzz bit has no effect.
0
No effect on buzz modes.
1
Buzz is disabled during sleep, with bandgap powered down. No periodic wakeup of the
bandgap during sleep.
5
No Buzz
This bit allows the bandgap to stay powered during sleep.
0
Buzz bandgap during power down.
1
Bandgap is always powered even during sleep.
4:3
Sleep[1:0]
Sleep interval.
For 32-kHz ILO
For 1-kHz ILO
00b
1.95 ms (512 Hz)
64 ms (15.6 Hz)
01b
15.6 ms (64 Hz)
512 ms (1.95 Hz)
10b
125 ms (8 Hz)
4 s (0.244 Hz)
11b
1s (1 Hz)
32 s (0.031 Hz)
2:0
CPU Speed[2:0]
These bits set the CPU clock speed, based on the system clock (SYSCLK). SYSCLK is 12 MHz by
default, but it can also be set to other frequencies (6 and 24 MHz), or driven from an external clock.
Note
During USB operation, the CPU speed can be set to any setting. Be aware that USB through-
put decreases with a decrease in CPU speed. For maximum throughput, the CPU clock should be
made equal to the system clock. The system clock must be 24 MHz for USB operation.
6-MHz IMO
12-MHz IMO
24-MHz IMO
External Clock
000b
750 kHz
1.5 MHz
3 MHz
EXTCLK/8
001b
1.5 MHz
3 MHz
6 MHz
EXTCLK/4
010b
3 MHz
6 MHz
12 MHz
EXTCLK/2 (Reset State)
011b
6 MHz
12 MHz
24 MHz
EXTCLK/1
100b
375 kHz
750 kHz
1.5 MHz
EXTCLK/16
101b
187.5 kHz
375 kHz
750 kHz
EXTCLK/32
110b
46.9 kHz
93.7 kHz
187.5 kHz
EXTCLK/128
111b
23.4 kHz
46.8 kHz
93.7 kHz
EXTCLK/256
Individual Register Names and Addresses:
1,E0h
OSC_CR0: 1,E0h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
RW : 0
RW : 010b
Bit Name
X32ON
Disable Buzz
No Buzz
Sleep[1:0]
CPU Speed[2:0]
Bit
Name
Description
