enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
91
I/O Analog Multiplexer
13.2
Register Definitions
The following registers are only associated with the Analog Bus Mux in the CY7C643xx and CY7C604xx enCoRe V devices
and are listed in address order. Each register description has an associated register table showing the bit structure for that
register. Register bits that are grayed out throughout this document are reserved bits and are not detailed in the register
descriptions that follow. Always write reserved bits with a value of ‘0’.
13.2.1
MUX_CRx Registers
The Analog Mux Port Bit Enable Registers (MUX_CR0,
MUX_CR1, MUX_CR2, MUX_CR3, and MUX_CR4) control
the connection between the analog mux bus and the corre-
sponding pin.
Bits 7 to 0: ENABLE[7:0].
The bits in these registers
enable connection of individual pins to the analog mux bus.
Each I/O port has a corresponding MUX_CRx register.
Setting a bit high connects the corresponding pin to the
analog bus.
For additional information, refer to the
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
1,D8h
ENABLE[7:0]
RW : 00
1,D9h
ENABLE[7:0]
RW : 00
1,DAh
ENABLE[7:0]
RW : 00
1,DBh
ENABLE[7:0]
RW : 00
1,DFh
ENABLE[3:0]
RW : 0
