manualshive.com logo in svg

Artison 75340-1, User Manual, Page: 70 / 482

Share
Download
Artison 75340-1 User Manual Download Page 70

Publication No. 980938  Rev. K    

 

Model T940 User Manual 

Astronics Test Systems 

 

Functional Description  4-5 

Linked 

Used to describe two sequencers (DSA and DSB) on the 
same DRM that are synchronized together. 

Primary 

Used to describe the DRM that provides all the timing for the 
sequencers that are part of the DRS chain.  DSA is always 
coupled to the DRS chain and is the source of the timing and 
control.  DSB can be coupled to the new chain or run 
independently from the chain.  The primary module must be 
located in the right most slot position in the VXI chassis 
relative to the DRMs that will be coupled. 

Secondary 

Used to describe the DRMs located between the primary and 
terminator module that pass the timing signals to the DRM in 
the next lower slot position.  Individual sequencers can be 
coupled to the DRS or run independently from the primary 
module as linked or not linked. 

Terminator 

Used to describe the DRM in the left most position of the DRS 
chain.  Individual sequencers can be coupled to the DRS or 
run independently from the primary module as linked or not 
linked. 

LBUSA 

VXI Local Bus A, used to connect adjacent modules.  

LBUSC 

VXI Local Bus C, used to connect adjacent modules.  

CONTROL 

Control signals used to set relay, driver and mux settings. 

IMA 

Inter-Module signals from DSA. 

SIMA 

Selected Inter-Module signal used by DSA.    

IMB 

Inter-Module signals from DSB. 

SIMB 

Selected Inter-Module signal used by DSB.    

IMJMPR 

T940 inter-module jumper.  This jumper sets the DRS mode as 
primary, secondary or terminator. 

Note:  Refer to DRS Inter-Module Mode Control in Chapter 2, Installation for 
information on the Inter-Module Control jumper settings. 

Description 

The DRM utilizes the following VXI backplane resources to enable adjacent 
DRMs to be synchronized together to form a DRS: 

•

  VXI Local Bus A/C (LBUSA/LBUSC) – Sequencer A on the primary module 

drives all twelve LBUSA signals (Phases, Windows, Clocks and Jump Flag). 
Both Sequencers can receive LBUSA and LBUSC signals. 

•

  VXI Triggers – Used for passing information between the DRS modules (e.g. 

error flag, synchronization flag, reset signal, driver disable signal, channel 
handshake) 

T940 Inter-Module Mode Settings 

The VXI

plug&play

 API function that sets the inter-module mode is 

“tat964_setModuleInterconnect”.  The valid settings with reference to figure 4-3 
are: 

Summary of Contents for 75340-1

Page 1: ...buy your excess underutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Ready to ship TAR certified secure asset solutions Expert team I Trust guarantee I 100 satisfaction All trademarks brand names and brands appearing herein are the property of th...

Page 2: ...el 800 722 2528 949 859 8999 Fax 949 859 7139 atsinfo astronics com atssales astronics com atshelpdesk astronics com http www astronicstestsystems com Copyright 2009 by Astronics Test Systems Inc Printed in the United States of America All rights reserved This book or parts thereof may not be reproduced in any form without written permission of the publisher ...

Page 3: ...ation s of any product or part without Astronics Test Systems express written consent or misuse of any product or part The warranty also does not apply to fuses software non rechargeable batteries damage from battery leakage or problems arising from normal wear such as mechanical relay life or failure to follow instructions This warranty is in lieu of all other warranties expressed or implied incl...

Page 4: ...fy procurement of products from Astronics Test Systems TRADEMARKS AND SERVICE MARKS All trademarks and service marks used in this document are the property of their respective owners Racal Instruments Talon Instruments Trig Tek ActivATE Adapt A Switch N GEN and PAWS are trademarks of Astronics Test Systems in the United States DISCLAIMER Buyer acknowledges and agrees that it is responsible for the...

Page 5: ...sion cord or a three prong two prong adapter This will defeat the protective feature of the third conductor in the power cord Maintenance and calibration procedures sometimes call for operation of the unit with power applied and protective covers removed Read the procedures and heed warnings to avoid live circuit points Before operating this instrument 1 Ensure the proper fuse is in place for the ...

Page 6: ... Model and Part Number Information 1 10 Accessories 1 12 Chapter 2 2 1 Installation 2 1 Initial Digital Board DB Switch Setting 2 2 Logical Address Selection 2 3 VXI Interrupt Selection 2 4 A24 A32 Map Selection 2 4 Other Settings 2 5 Debug Selection 2 5 Mode Selection 2 5 Bus Request Selection 2 6 DRS Inter Module Mode Control 2 6 Installing the Module into a VXI Chassis 2 7 Initial Power On 2 10...

Page 7: ...Settings 4 5 Examples 4 7 Data Sequencer 4 10 Terms Used in this Section 4 11 Sequence Logic 4 13 Master Clock 4 13 System Clock 4 14 Test Logic 4 14 Record Control 4 14 Trigger Logic 4 14 Counter Timer Pulse Generator 4 14 Sequence Controller 4 14 Timers 4 14 Probe Flag RAM 4 14 Pattern RAM 4 15 Record RAM 4 15 Frequency Synthesizer 4 15 Sequence Control 4 15 Channel Control 4 15 AUX Probe Contro...

Page 8: ...ked Trigger Bus 5 13 LTBn Signal 5 14 Invert 5 15 Direction 5 15 Group 5 15 Group Attributes 5 15 Offset 5 16 IO Min 5 16 IO Max 5 16 Slew 5 16 OC Src 5 17 OC Sink 5 17 Update Group Settings 5 17 Group 1 3 5 18 Delay Signal 5 18 Delay 5 18 VXI Triggers 5 18 TTLTRG and ECLTRG Signal 5 19 Invert 5 20 D R Properties 5 20 DUT_GND 5 21 Voltage Mode 5 21 MFSIG Source 5 22 MPSIG Signal 5 22 Error Pulse W...

Page 9: ...5 33 Input Mode 5 34 Edge Test Clear 5 34 Configure Pulse Generator 5 35 Resolution 5 35 Mode 5 35 Step 5 36 Period 5 36 Delay 5 36 Width 5 37 Configure Data Sequencer Settings 5 37 Error Record Basis 5 38 Raw Record Basis 5 38 Record Offset 5 38 Record Type 5 39 Error Count Basis 5 39 Error Address Basis 5 40 Timing Mode 5 40 Output to Input Disable 5 41 Pass Fail Basis 5 41 Pass Valid Mode 5 42 ...

Page 10: ... Configuring the I O Channels 5 53 Selecting the Channels 5 53 Channel Parameters 5 54 Stimulus Signal 5 54 Stimulus Format 5 55 Capture Signal 5 56 Capture Mode 5 57 Static Mode 5 57 Properties 5 58 Configure Channel Properties 5 58 Driver Levels 5 59 Comparator Levels 5 60 Driver Slew 5 60 Termination 5 60 Over Current Alarm Levels 5 61 Active Load 5 61 Channel Connect 5 63 Hybrid Connect 5 63 C...

Page 11: ...ules 5 76 Advanced Timing Set Features 5 76 Phase Window Spanning 5 77 Idle Standby Timing 5 77 Editing the Patterns 5 77 Append 5 78 Assign 5 79 Edit Data 5 80 Import Export File Format 5 87 Header Format 5 87 Data Format 5 87 ASCII Hex 5 87 Binary 5 89 ASCII String 5 90 Editing Waveforms 5 90 Table Size 5 91 Waveform 5 92 Table Number 5 92 Waveform Definition 5 92 Editing Sequence Parameters 5 9...

Page 12: ...105 Vector Jump 5 105 Pass Fail Clear 5 105 Step Record Mode 5 105 Timing 5 106 Patterns 5 107 Properties 5 109 Handshake Control 5 109 Pause Signal 5 109 Resume Modifier 5 110 Waveform Properties 5 111 Waveform1 Waveform4 5 111 Waveform Table 5 111 Phase Trigger Properties 5 111 Execute the Sequence 5 112 Execution Overview 5 113 Execute Panel Indicators 5 115 Idle LED 5 115 Active LED 5 115 Halt...

Page 13: ...Offset 5 122 Length 5 123 Execute Panel Command Buttons 5 123 Execute Idle 5 123 Execute 5 123 Halt 5 123 Resume 5 124 Stop 5 124 Reset 5 124 Master Reset 5 124 Deskew 5 124 Arm PG 5 124 Stop PG 5 125 Analyze the Execution Results 5 125 Static Data 5 125 Stimulus Delay 5 126 Response Delay 5 126 Stimulus 5 127 Response 5 127 Kept Data 5 127 Results 5 128 View 5 129 Save Results 5 129 CRC Save File...

Page 14: ... 5 143 Status 5 144 Driver Receiver Events Panel 5 144 Enable 5 147 Condition 5 147 Event 5 147 Clear Event 5 147 Alert Text 5 147 Driver Receiver Data Panel 5 148 VXI Trigger Readback Panel 5 150 Query Power Results Message 5 150 Power Converter Condition Panel 5 151 Counter Timer Panel 5 152 Function 5 152 Input 1 3 Source 5 153 Input 1 3 Slope 5 154 Aperture 5 154 Trigger 5 154 Initiate 5 155 R...

Page 15: ...RCE 5 170 EXTSENSE 5 170 Channel 5 170 Monitor Signal 5 170 Monitor Voltage 5 171 DR4 Voltage Monitor Panel and Controls 5 171 Mux Signal 5 171 Channel 5 171 Monitor Voltage 5 171 Mode 5 172 Positive Signal 5 172 Negative Signal 5 172 AD Signal 5 172 CD Signal or E_S Signal 5 172 Register 5 172 Value 5 173 Chip Temperature Panel 5 173 Utility Reference Monitor 5 174 Monitor Signal 5 175 SFP Close ...

Page 16: ...t and End Channels and Measurement Delay 6 14 DRM Calibration Warmup 6 14 Run Calibration 6 14 CVH CVL 6 15 Select Calibrate Function 6 15 Select Start and End Channels and Measurement Delay 6 16 DRM Calibration Warmup 6 16 Run Calibration 6 17 Vcom High Low 6 18 Select Calibrate Function 6 18 Select Start and End Channels and Measurement Delay 6 18 DRM Calibration Warmup 6 19 Run Calibration 6 19...

Page 17: ...Counting and Logging Errors 8 9 Pipelining and non Pipelining 8 13 Jumping and Halting on Pass Fail 8 14 Understanding Pass and Fail 8 18 Additional Pipeline Information 8 23 Valid Pass and Capture Fault 8 24 Additional Halt Information 8 24 Pipelined Depth Calculation 8 26 Pause and Halt Capabilities 8 27 Definitions 8 27 Applications 8 27 CPU Halt Single Stepping Resume Operations 8 27 External ...

Page 18: ...e NV Data B 5 Signal Descriptions B 5 DR1 Characteristics B 5 Power Requirements B 6 Environmental B 6 DR1 Signal Description B 7 DRA I O Channels J200 B 7 DRB I O Channels J201 B 9 PWR Connector B 11 Calibration B 12 Appendix C C 1 DR2 Driver Receiver Board C 1 DR2 Features C 1 Front Panel Connectors C 1 Block Diagram C 1 Auxilliary Driver Receiver I O C 2 Signal Descriptions C 3 DR2 Driver Recei...

Page 19: ... D 7 DR3e Characteristics D 8 I O Min Max Levels D 9 Power Requirements D 10 Environmental D 11 DR3e Signal Description D 12 DRA I O Channels J200 D 13 DRB I O Channels J201 D 15 PWR Connector D 17 Calibration D 18 Appendix E E 1 DR4 Driver Receiver Board E 1 DR4 Features E 1 Front Panel Connectors E 1 Block Diagram E 1 Signal Descriptions E 3 Channel Driver Receiver I O E 4 Signal Descriptions E ...

Page 20: ...equirements F 6 Environmental F 6 DR7 Signal Description F 7 DRA I O Channels J200 F 7 DRB I O Channels J201 F 10 Calibration F 10 Appendix G G 1 DR8 Driver Receiver Board G 1 DR8 Features G 1 Front Panel Connectors G 1 Block Diagram G 1 Auxiliary Driver Receiver I O G 2 Signal Descriptions G 3 DR8 Driver Receiver I O G 4 Signal Descriptions G 4 Control Logic G 4 Signal Descriptions G 4 Firmware N...

Page 21: ...esources H 16 J9 Connectors H 18 Calibration H 19 Appendix I I 1 UR14 Driver Receiver Board I 1 UR14 Features I 1 Block Diagram I 1 Auxiliary Driver and Receiver I O ECL LVTTL I 4 Signal Descriptions Figure I 3 I 5 Signal Descriptions Figure I 4 I 6 Signal Descriptions Figure H 5 I 7 Probe I O I 8 Signal Descriptions Figure I 6 I 8 Programmable Driver and Receiver I O I 10 Signal Descriptions Figu...

Page 22: ... DRM Timing Characteristics J 1 Introduction J 1 External AUX Input Timing Adjustments J 1 External AUX Output Timing Adjustments J 2 TRG Input Timing Adjustments J 2 TRG Output Timing Adjustments J 2 AUX Input to TRG J 2 TRG Input to AUX Output J 2 DRS Timing Adjustments J 2 External T0CLK to T0CLK In at min delay setting J 2 External Halt Setup Time to SEQ_CLK Out J 3 External Pause to CLK Cease...

Page 23: ...Model T940 User Manual Publication No 980938 Rev K xviii Astronics Test Systems This page was left intentionally blank ...

Page 24: ...nnector 3 3 Figure 3 4 LBUS Lockout Keys 3 4 Figure 3 5 LBUS Lockout Configuration 3 5 Figure 4 1 T940 DRM Block Diagram 4 1 Figure 4 2 T940 VXI Bridge Block Diagram 4 2 Figure 4 3 T940 Inter Module Control Block Diagram 4 4 Figure 4 4 Data Sequencer Block Diagram 4 10 Figure 4 5 Sequencer Logic Block Diagram 4 13 Figure 5 1 Reset Screen 5 2 Figure 5 2 Initialize Warning 5 2 Figure 5 3 Main Panel ...

Page 25: ...equencer Timing Sets Panel 5 75 Figure 5 41 Edit Patterns Panel 5 78 Figure 5 42 Append Data Sequencer Pattern Sets Panel 5 79 Figure 5 43 Assign Data Sequencer Pattern Sets Panel 5 80 Figure 5 44 Pattern Set Sequencer Data Panel 5 81 Figure 5 45 Pattern Set Data View Menu 5 81 Figure 5 46 Goto Pattern Panel 5 82 Figure 5 47 Pattern Codes 5 82 Figure 5 48 Probe Codes 5 83 Figure 5 49 Pattern Set D...

Page 26: ...n Panel 5 151 Figure 5 84 Timer Counter Panel 5 152 Figure 5 85 PMU Panel 5 155 Figure 5 86 Self Test Result Message 5 156 Figure 5 87 Full RAM Test Results Panel 5 158 Figure 5 88 Power Converter Test Results Panel 5 159 Figure 5 89 Calibration Confirmation Panel 5 160 Figure 5 90 Calibration Panel 5 160 Figure 5 91 Confirm Calibrate Panel 5 162 Figure 5 92 Calibrate Warm up Panel 5 162 Figure 5 ...

Page 27: ...ure 8 13 Setting the Jump Condition in the Edit DSA Sequence Step Panel 8 17 Figure 8 14 Setting the Halt Mode in the Execute DSA Panel 8 18 Figure 8 15 Setting the Halt Mode in the Execute DSA Panel 8 19 Figure 8 16 Setting the Pass Fail Clear Control in the Edit DSA Sequence Step Panel 8 21 Figure 8 17 Setting the Jump Pass Fail Mode in the DSA Advanced Options Panel 8 22 Figure 8 18 Setting the...

Page 28: ...iagram H 4 Figure H 4 DR9 Driver Receiver I O Block Diagram H 5 Figure H 5 DR9 Control Logic Block Diagram H 7 Figure H 6 DR9 J1A J1B J2A J2B J3A and J3B Signal Connectors H 13 Figure I 1 UR14 Front Panel I 2 Figure I 2 UR14 Driver Receiver Block Diagram I 3 Figure I 3 Auxiliary AUX3 A AUX 5 12 A LVTTL DIFF ECL I O I 4 Figure I 4 Auxiliary AUX 5 8 B LVTTL SE ECL I O I 6 Figure I 5 Auxiliary AUX 9 ...

Page 29: ...Model T940 User Manual Publication No 980938 Rev K xxiv Astronics Test Systems This page was left intentionally blank ...

Page 30: ... Descriptions 5 9 Table 5 7 Inter Module Types 5 11 Table 5 8 Inter Module Mode Settings 5 12 Table 5 9 Power Converter Ranges 5 13 Table 5 10 LTB Signal Pull Down Settings 5 14 Table 5 11 Direction Settings 5 15 Table 5 12 Group Offset Attribute Settings 5 16 Table 5 13 Group Slew Attribute Settings 5 17 Table 5 14 Delay Signal Settings 5 18 Table 5 15 Signal Pull Down Settings 5 19 Table 5 16 Vo...

Page 31: ...on Settings 5 47 Table 5 48 Probe Cal Signal Settings 5 48 Table 5 49 Jump Pass Fail Settings 5 50 Table 5 50 Phase 3 Mode Settings 5 51 Table 5 51 Window 3 Mode Settings 5 51 Table 5 52 CRC Preload Settings 5 52 Table 5 53 CRC Algorithm and Mask Settings 5 52 Table 5 54 Static State Settings 5 53 Table 5 55 Stimulus Signal Settings 5 54 Table 5 56 Stimulus Format Settings 5 55 Table 5 57 Capture ...

Page 32: ...View Settings 5 129 Table 5 95 Probe Memory Bit Descriptions 5 136 Table 5 96 Sequence Enable Condition Event Bit Descriptions 5 140 Table 5 97 Sequence Status Bit Descriptions 5 144 Table 5 98 Sequence Status Bit Descriptions 5 145 Table 5 99 Sequence Status Bit Descriptions 5 146 Table 5 100 Alert Bit Descriptions 5 148 Table 5 101 Counter Timer Function Settings 5 153 Table 5 102 Counter Timer ...

Page 33: ... PWR Connector C 13 Table C 8 Calibration Settings C 13 Table D 1 DR3e Characteristics D 8 Table D 2 DR3e I O Min Max Levels Front Panel D 9 Table D 3 DR3e I O Min Max Levels Power Converter Type 1 or 3 D 10 Table D 4 VXI Power Requirements with Front Panel Power D 10 Table D 5 VXI Power Requirements not including Power Converter power consumption D 10 Table D 6 DR3e DRA I O Channels J200 D 13 Tab...

Page 34: ...ber H 16 Table H 11 2B Connector Pinout by Pin Number H 16 Table H 12 J1B Connector Pinout by Pin Number H 17 Table H 13 J9A Pinout H 18 Table H 14 J9B Pinout H 18 Table I 1 External Probe Module Characteristics I 19 Table I 2 Utility Channel Characteristics I 20 Table I 3 Programmable Channel Characteristics I 21 Table I 4 Programmable AUX I O Min Max Levels Front Panel I 23 Table I 5 Programmabl...

Page 35: ...14 board and probe features F 7 23 2013 ECN03095 Added information regarding DR8 option G 5 7 2014 ECN04897 Added additional content including attributes and static state control statis mode comparator delay pass fail clear and static data Revised MTBF hours for boards Rebranded manual to Astronics H 6 13 2014 ECN05018 Added information regarding new DR4 option including Appendix E DR4 Driver Rece...

Page 36: ...ata sequencers and up to 64 high performance digital I O channels in a space saving single wide VXI module The DRM operates at data rates up to 50 MHz with 1 ns edge placement and less than 3 ns channel to channel skew Designed for High Reliability The comprehensive thermal design ensures reliability with excellent cooling monitoring and protection Each high power module is equipped with a custom ...

Page 37: ...ng TPS Investments The DRM is ideal for replacing less reliable obsolete instruments With the innovative software tools the investments in digital technology can be preserved and sustained going forward on a modern platform Legacy TPS performance has been demonstrated on ARGCS RTCASS NGATS ESTS B 1B ARTS and used to replace L300 legacy systems Scalable Design Built in scalability and modular desig...

Page 38: ...e provides the capability for the DRM to support both legacy and modern system implementations that take advantage of the higher order signal oriented features of IEEE ATLAS The interface utilizes the PAWS system the popular independent implementation of the ATLAS language The user does not need to know the nuances of the DRM as the ATLAS language provides the higher order interface to the hardwar...

Page 39: ... ground or both Direct or 100 ohm selectable output impedance Auxiliary channels Four LVTTL with selectable output impedance and resistive input load Four LVTTL Four ECL single ended or differential DR2 Driver Receiver The DR2 features Channels 32 differential LVDS Auxiliary channels Four LVDS Four LVTTL Four ECL single ended or differential DR3e Driver Receiver The DR3e features Channels 32 singl...

Page 40: ...tection Temperature monitoring 16 TTL auxiliary channels DR7 Driver Receiver The DR7 features Channels 32 differential RS 422 485 Auxiliary channels Four RS 422 485 Four LVTTL Four ECL single ended or differential DR8 Driver Receiver The DR8 features Channels 32 single ended TTL Relay Isolation on all I O and AUX channels Selectable resistive input load to VCC 5 0 V ground or both Direct or 100 oh...

Page 41: ...ce module type available UR14 Utility Resource The UR14 features Channels 32 Low Speed single ended open collector utility pins Voltage range 0 to 30 V Suitable for Inductive loads internal clamping to 42 V 5 V Pull up allowing each channel to operate as low speed TTL Programmable input level detection per byte 0 20 V Programmable over current detection per byte 0 1 A External probe support Auxili...

Page 42: ...ny of the DR boards such as DR1 DR2 DR3e etc offered for the DRM system Figure 1 1 Example DRM with Two Driver Receiver Boards DRA and DRB If the DRM has only one Driver Receiver board the front panel will have a blank cover panel where the front connector would have been located Note The DR9 board has a different front connector panel than the others Refer to Appendix H for more information about...

Page 43: ...he device being tested There is a Driver Receiver board connector for input and output of signals As an option the T940 can be equipped with an external power connector to power the DR3e Figure 1 3 T940 Optional Front Panel PWR Connector DRIVER RECEIVER DRA VXI BRIDGE INTER MODULE CONTROL DRIVER RECEIVER DATA SEQUENCER DRB DSA DATA SEQUENCER DSB DIGITAL BOARD DB FRONT PANEL POWER CONVERTER PC OPTI...

Page 44: ...The DRM functions are programmed through VXI A16 A32 A24 register access Inter Module Control In a multi module system the VXI Local Bus is used to synchronize the modules The Inter Module Control logic is used to route and terminate these signals Data Sequencer A and B Each DB contains two Data Sequencers DSA and DSB Each data sequencer can be run independently or synchronized Data Sequencer A pr...

Page 45: ...DR2 LVDS 32 channels 100 Ω source termination 405350 DR3e Variable voltage 15 V to 24 V 32 Channels 408002 DR4 Variable voltage 31 V to 31 V 48 Channels 408558 DR7 RS422 RS485 32 channels 100 Ω source termination 408242 101 DR8 TTL 32 channels 100 Ω source termination 408241 101 TTL 32 channels 50 Ω source termination 408241 102 DR9 Variable voltage 15V to 24V 24 Direct Analog Test Channels 408254...

Page 46: ...8291 Model Code A Power Converter Code Description Specify for DR3e or DR9 Spares Part Type 1 1 VXI 3 0 power converter 24V 405404 001 Type 3 3 VXI 4 0 power converter 24V 405404 003 Type 4 4 VXI 3 0 or 4 0 power converter 16V 405404 004 Model Code W Installed CIB or Funnel Code Description Spares Part Type F F VP90 Style Coaxial Funnel available for DR9 and UR14 DR9 408257 UR14 408258 Type F1 F1 ...

Page 47: ...ons 3 unterminated 408125 XXX NA T940 Coaxial IDC Cable 17 positions both ends IDC terminated 4 per 64 channel module used with DR9 and DR3e modules 602715 XXX N A A C type LBUS Lockout Key 455540 N A C type LBUS Lockout Key 455541 N A T940 Inter Module Mode Jumper 408382 N A External Probe Module Right Angle 405389 001 N A External Probe Module Flush 405389 002 N A External Probe Module Handheld ...

Page 48: ...ess and mode settings to your test situation Refer to the next several sections for this setup information If you have received a small packet of extra screws with the module place these in a secure location for future use should you add a Driver Receiver board at a later date WARNING The DRM is NOT hot swappable The power to the VXI chassis must be turned off before installing a DRM Plugging the ...

Page 49: ...hree DIP switches on the Digital Board located between the VXI connectors P1 and P2 at the rear end of the board When shipped they are set to current factory default settings However SW1 and SW2 can be set to modify several selections including Logical Address Selection VXI Interrupt Level Selection A24 A32 Map Selection If you are using two or more T940 boards in a system there is also a jumper t...

Page 50: ... or dynamically configured SW1 an eight position DIP switch located on the DB Figure 2 3 is used to assign the logical address Refer to Table 2 1 A switch setting between 1 and 254 will establish a static logical address of the binary encoded value A switch setting of 255 will place the DRM in a dynamic logical address mode where the final logical address is assigned by the resource manager A swit...

Page 51: ...interrupt level 6 will be used by the DRM VXI level one is set at the factory prior to shipment Table 2 2 VXI Interrupt Selection SW2 Position 8 7 6 Signal ILEV0 ILEV1 ILEV2 ILEV2 ILEV1 ILEV0 VXI Interrupt Level OFF OFF OFF Disabled none OFF OFF ON Level 1 Selected factory default OFF ON OFF Level 2 Selected OFF ON ON Level 3 Selected ON OFF OFF Level 4 Selected ON OFF ON Level 5 Selected ON ON OF...

Page 52: ... that are used for development or debug which under normal operation should not be changed The factory set default setting for normal operation is noted in each case Debug Selection This is a factory setting and must be set OFF for normal operation Switch position 4 of SW2 is used to select debug operation Table 2 4 Debug Selection SW2 Position 4 Signal DEBUG DEBUG Debug Operation OFF Debug off De...

Page 53: ...8382 to define whether the DRM is the Primary Secondary or Terminator A T940 DRS is configured right to left The Primary must be installed to the right of the Terminator Secondary DRMs if any are placed between the Primary and Terminator The Inter Module Control section in Chapter 4 Functional Description describes this feature in detail The Inter Module Mode section in Chapter 5 Soft Front Panel ...

Page 54: ...n Primary Position Note The gray areas in the figure indicate the open portions of the connector Figure 2 5 T940 Inter Module Mode Jumper Positions and Settings Installing the Module into a VXI Chassis WARNING The DRM is NOT hot swappable The power to the VXI chassis must be turned off before installing a DRM Plugging the module in before the power is off may result in damage to the electronics Ju...

Page 55: ...les are installed into the same chassis The DRM may be installed in any VXI chassis slot except slot 0 zero which is reserved for the Resource Manager See Figure 2 6 Always check VXI connectors P1 and P2 for bent pins prior to installation When inserting the DRM into the chassis it should be gently rocked back and forth to seat the connectors into the backplane receptacles Figure 2 6 Installing th...

Page 56: ...13 slot VXI chassis series Figure 2 7 is recommended for multiple DRMs which are populated with multiple DR3e DR4 or DR9 modules These chassis have an integrated power supply and enhanced cooling that will support such DRMs For information on these products contact your Astronics Test Systems sales representatives Any VXI chassis will support a DRM that is populated with DR1s DR2s DR7s DR8s or UR1...

Page 57: ... is properly installed in the chassis and turn the chassis power back on Should the DRM continue to fail perform the following or contact Customer Support for assistance 1 Install the instrument driver see next section 2 Run the Soft Front Panel program and select Instrument Self Test Should the Soft Front Panel self test continue to fail contact Customer Support for assistance Customer Support co...

Page 58: ...There are two versions of the driver installer on the CD one with the Run Time Engine RTE and one without The installer with the RTE is in the Driver with RTE folder The installer without the RTE is in the Driver without RTE folder 3 Double click the setup exe file 4 Follow the setup directions After the instrument driver is installed the DRM soft front panel will be launched The following files a...

Page 59: ...Model T940 User Manual Publication No 980938 Rev K Installation 2 12 Astronics Test Systems This page was left intentionally blank ...

Page 60: ...Front Panel The DRM front panel provides the hardware interface to the unit under test UUT Figures 3 1 and 3 2 illustrate the front panel and its connectors Figure 3 1 T940 Front Panel Appearance Typical DRB Channel I O J201 T940 shown with two Driver Receiver boards installed DRA and DRB DRA Channel I O J200 ...

Page 61: ...boards that are installed Refer to the Appendix of the specific DR board for connector interface information PWR Connector DRA DRB Power and Signals The PWR connector is an option on the T940 which is used to supply external power to DR3e Driver Receiver boards and can be used to supply DRB Channel I O J201 DRA DRB Power and Multi Function Signals on this optional connector DRA Channel I O J200 T9...

Page 62: ...rt and ordering numbers for the DRM cable assemblies Table 3 2 Mating Connector Part Numbers Connector Manufacturer Part Number ATS Order Number J200 J201 mate 3M 101A0 6000EC 40892 J200 J201 flat cable backshell for the above 3M 103A0 12R1 00 Included with 40892 PWR Amphenol T3505 001 408091 Table 3 3 Cable Assembly Part Numbers Description ATS Order Number T940 coaxial cable 17 positions both en...

Page 63: ...d to the exterior of the module at the top of the front panel Figure 3 4 illustrates the two types of LBUS Lockout Keys used for this product Figure 3 5 shows the application of Lockout Keys for the T964 A C type C type Figure 3 4 LBUS Lockout Keys The LBUS Lockout Key is fitted to all modules The T964 requires the use of the A C type LBUS Lockout Key PN 455540 on all modules The T940 may use the ...

Page 64: ...install lockout keys to the module 1 Set the module ejector handle to the un ejected position 2 The first key may be pushed around the ejector handle and aligned with the front panel screw holes This takes up most of the clearance under the ejector handle preventing the second lockout key from being installed To provide the necessary clearance move the first lockout key away from the module body a...

Page 65: ...v K DRM Front Panel 3 6 Astronics Test Systems 2 Install two screws in the holes at the top of the module front panel and tighten the screws 3 Move the ejector handle to the ejected position and install a third screw in the hole now made accessible ...

Page 66: ... POWER CONVERTER INTER MODULE CONTROL VADDR VXI TRIGGERS VXI_INT AUX 1 12 A VXI POWER PROBE MODE A PROBE BUTTON A LBUSA LBUSC CH 1 32 GNDREFA DUTGNDA MONITORA MISCA AUX 1 12 B PROBE MODE B PROBE BUTTON B CH 33 64 GNDREFB DUTGNDB MONITORB MISCB DATA SEQUNCER DSA DATA SEQUNCER DSB DRIVER RECEIVER DRA DRIVER RECEIVER DRB VCTRL J200 J201 V V VDATA 500 MHz Figure 4 1 T940 DRM Block Diagram The followin...

Page 67: ...ver Receiver board s Control Logic JTAG Joint Test Action Group IEEE 1149 1 Serial interface that allows the serial PROM to be reloaded for in field system upgrades I2C Inter Integrated Circuit Multi master serial interface that allows communication to the temperature monitor and EEPROM Description The main purpose of the VXI Bridge is to provide a communication interface between the VXI backplane...

Page 68: ...Table 4 1 Power Converter Type 1 and Type 3 Ranges Range V Nominal Voltage V Nominal Voltage 12 to 12 16V 15 6V 15 to 5 9 6V 19 2V 10 to 10 16V 14 1V 5 to 7 12V 9 6V 5 to 15 19 2V 9 6V 0 to 22 28 8V 4 5V 2 to 20 26 4V 6V Type 4 The type 4 power converter has a reduced voltage range and better power distribution of the VXI backplane supplies Table 4 2 Power Converter Type 004 Ranges Range V Nominal...

Page 69: ...Control IMJMPR IMJMPR 3 3V IMJMPR Figure 4 3 T940 Inter Module Control Block Diagram Terms Used in this Section DRM Digital Resource Module A DRM is a single T940 module A DRM is comprised of a Digital Board DB and one or two Driver Receiver boards DRA and DRB DRS Digital Resource Suite A DRS is two or more adjacent DRMs synchronized together to form a digital test system with more than 64 channel...

Page 70: ...le as linked or not linked LBUSA VXI Local Bus A used to connect adjacent modules LBUSC VXI Local Bus C used to connect adjacent modules CONTROL Control signals used to set relay driver and mux settings IMA Inter Module signals from DSA SIMA Selected Inter Module signal used by DSA IMB Inter Module signals from DSB SIMB Selected Inter Module signal used by DSB IMJMPR T940 inter module jumper This ...

Page 71: ...sabled The DRM is not coupled to a DRS DSA and DSB are not linked Independent Linked SIMA and SIMB set to IMA IMJMPR position is a don t care Primary driver disabled The DRM is not coupled to a DRS DSA and DSB are linked Secondary Not Linked SIMA set to IMA and SIMB set to IMB IMJMPR position set to secondary LBUSA connected to LBUSC Primary driver disabled The DRM is coupled to a DRS DSA and DSB ...

Page 72: ...r DSA Coupled SIMA set to LBUSC and SIMB set to IMB IMJMPR position set to terminator LBUSC connected to termination Primary driver disabled DSA is coupled to a DRS DSB is independent Terminator DSB Coupled SIMA set to IMA and SIMB set to LBUSC IMJMPR position set to terminator LBUSC connected to termination Primary driver disabled DSB is coupled to a DRS DSA is independent Terminator DSA and DSB ...

Page 73: ...annels Three Groups of 128 Channels Module T940 Configuration M1 Primary Linked M2 Terminator DSA and DSB Coupled M3 Primary Linked M4 Terminator DSA and DSB Coupled M5 Primary Linked M6 Terminator DSA and DSB Coupled DRM6 DRM5 DRM4 DRM3 DRM2 DRM1 CH 1 64 CH 65 128 CH 129 192 CH 193 256 CH 257 320 CH 321 384 SEC SEC SEC SEC TER SEC TER LINKED COUPLED PRI DSB DSA DSB DSA DSB DSA DSB DSA DSB DSA DSB...

Page 74: ...re coupled to a third DRS 128 channels Two Groups of 128 Channels One Group of 64 Channels and Two Groups of 32 Channels Module T940 Configuration M1 Primary Linked M2 Terminator DSA and DSB Coupled M3 Primary Linked M4 Terminator DSA and DSB Coupled M5 Secondary Linked M6 Terminator Not Linked DRM6 DRM5 DRM4 DRM3 DRM2 DRM1 CH 1 64 CH 65 128 CH 129 192 CH 193 256 CH 257 320 CH 321 384 SEC SEC SEC ...

Page 75: ...Sequencer PROBE FLAG RAM RECORD RAM PATTERN RAM SEQUENCE LOGIC FREQUENCY SYNTHESIZER SEQUENCE CONTROL CBUS PHASE CHANNEL CONTROL AUX PROBE CONTROL CH DATA CH EN CH RH CH RL CH OC AUX DATA AUX EN AUX RH AUX RL1 MPSIG PATADDR RECADDR PRBADDR PATADDR RECADDR FS 500MHz SIM WINDOW FS FLAGS PRB DATA FLAGS ERROR FS CH IN ERR IN AUX I O CH IN DB DR CONTROL PCODE DATA SEQUENCER IM IM CONTROL PRBADDR LTB CH...

Page 76: ...TA Channel output data value CH EN Channel output enable value CH IN Channel input data which is the response data CH IN ERR IN Channel input data which is either the response data or the input pattern code test result CH OC Channel output over current flag CH RH Channel input response high comparator result CH RH Channel input response low comparator result CONDEN Condition Enable A qualifier for...

Page 77: ...a PRBADDR Probe flag address used by the external RAM RECADDR Record address used by the external record RAM RESUME Sequence trigger used to resume a paused timing generator for handshaking applications SEQ Sequence Controller signals that can be assigned to the VXI or LTB Probe Button Sequence Flag 1 Sequence Flag 2 Idle Active Sequence Active SEQ CLK Sequence Clock SEQ JUMP Signal that a valid j...

Page 78: ...by the probe logic Sequence Logic DATA SEQUENCER SEQUENCE LOGIC AUX I O T0 CLK SEQ CLK SYNC 1 2 SEQ PG TRIGGER LOGIC AUX I O CHT 1 4 VXI TRIGGERS SYSTEM CLOCK 500MHz FS MCLK MASTER CLOCK FS ECLTRG0 PG TIMERS WATCHDOG SEQ TO PAT TO PAT DEL 1 2 LTB TIMING WAVEFORM GENERATOR SIM SEQ TRIG IM MCLK WINDOW PHASE SEQ CLK IMSEQ SEQUENCE CONTROLLER PRBADDR PATADDR T0 CLK PHASE COUNTER TIMER PULSE GENERATOR ...

Page 79: ...lse generator can be used to generate triggers system clock or as a AUX output signal The counter timer can be used to measure frequency or time interval data from any channel or AUX input Sequence Controller This block contains the Sequence RAM which defines the order in which Patterns will be output input As such this block provides the addressing to the Pattern RAM and the Record RAM The Sequen...

Page 80: ...RAM formats it and outputs it according to the phase timing PHASE The resultant drive CH DATA and enable CH EN signals go to the Driver Receiver logic The response high CH RH and response low CH RL signals from the Receivers are examined and then based on the window timing WINDOW the response is analyzed with respect to the input code The channel results are routed to the Record RAM The cumulative...

Page 81: ...ems Driver Receiver The DRM can accommodate two Driver Receiver boards named DRA or DRB for their mounted location Each Driver Receiver board contains unique driver receiver circuitry and front panel connector pinouts that are described in an appendix dedicated to each specific Driver Receiver type ...

Page 82: ...et sequence parameters e Edit sequence steps 5 Execute the sequence 6 Utilize status and post process functions to evaluate analyze results 7 Close the VXI DRM session The following sections describe the SFP operation as it pertains to the previous seven steps Additionally sections are included covering the instrument functions self test calibration and utility functions The relevant VXIplug play ...

Page 83: ... a single DRM in the system Once a single DRM is selected a dialog box prompts the user if the DRM should be reset Resetting the DRM clears any previously programmed settings Selecting No retains all the DRM structures and settings previously programmed Figure 5 1 Reset Screen The following warning will display if a DRM module with a type 3 power converter is installed in a VXI 3 0 chassis Figure ...

Page 84: ...80938 Rev K Model T940 User Manual Astronics Test Systems Soft Front Panel Operation 5 3 Figure 5 3 Main Panel Figure 5 4 Main Panel UR14 Company Logo Chassis Data Active LED Module Data Module Data Title Bar Menu Bar ...

Page 85: ...panel Figure 5 5 Company Information Panel Active LED The Active LED indicates whether a VXI session has been established successfully Chassis Data The chassis data control indicates the slot position and logical address of the DRM that the SFP is connected to Module Data The module data is displayed in four separate controls The module data is stored in non volatile memory Title Bar The title bar...

Page 86: ...sed to manage the loading and saving of test files With this menu DRM SFP project files are created loaded saved and renamed There are also diagnostic loads register dumps and calibration data loads A file history list permits quick reloading of recently accessed test files The SFP can also be closed from this menu Table 5 1 File Menu Descriptions Menu Option Description New Clears the DRM hardwar...

Page 87: ...an ASCII file Dump DRB Register Data Saves the register contents of the DRB Pin Electronics devices to an ASCII file Load DRA Calibration Loads calibration data for the DRA Driver Receiver board tat964_loadCalibrationFile Load DRB Calibration Loads calibration data for the DRB Driver Receiver board tat964_loadCalibrationFile Load DRM Data Loads the DRM data tat964_loadDrmFile Close Closes the DRM ...

Page 88: ... 5 9 Edit Menu Table 5 3 Edit Menu Descriptions Menu Option Description Data Sequencer A Displays the panels for programming DSA timing sets patterns sequence parameters and sequence steps Data Sequencer B Displays the panels for programming DSB timing sets patterns sequence parameters and sequence steps Execute Menu The Execute Menu is used to program the run option and run the sequences Figure 5...

Page 89: ... Description Self Test Runs the self test Full RAM Test Runs the full RAM test Calibrate Displays the calibration panel Update Flash Displays a file select dialog to select the Flash update file Temp Monitor Displays the temperature monitor panel Voltage Monitor Displays the voltage monitor panel Chip Temperature Displays the chip temperature panel Help Menu The Help Menu is used to open the instr...

Page 90: ...ontents About DRM Displays revision data for the DRM Soft Front Panel executable Figure 5 13 About DRM Driver Screen Opening a VXI DRM Session Starting the SFP initiates a search for all DRMs using the VISA library Once all the DRMs have been identified a selector panel will display only if more than one DRM is found Selecting one of the modules opens a VXI session with that module and then displa...

Page 91: ...64_autoConnectToSlot Configuring the Global Hardware Parameters Configuring the global hardware parameters is done from three panels Configure Module Configure Data Sequencer A and Configure Data Sequencer B Configure Module Panel Access this panel from the menu bar Config Module The Configure Module panel is used to program the inter module mode power converter mode state Linked Trigger bus routi...

Page 92: ...per is not installed the DRM can only be configured as Independent Not Linked or Independent Linked The DRM uses the VXI local bus signals to link multiple modules together The inter module configuration options consist of the types shown in Table 5 7 Table 5 7 Inter Module Types DRM Type Description Independent Independent modules do not pass the local bus chain and must not be placed between a P...

Page 93: ...ry DSB Coupled DSB coupled to DRS and DSA independent 5 Secondary DSA and DSB Coupled Both DSA and DSB coupled to the DRS Terminator The Terminator module is the DRM leftmost slot Five Terminator modes exist 1 Terminator Not Linked DSA and DSB not linked and are independent 2 Terminator Linked DSA and DSB linked and independent 3 Terminator DSA Coupled DSA coupled to DRS and DSB independent 4 Term...

Page 94: ... levels so that the driver receiver boards can operate over the specified range The On Off toggle switch enables disables the power converter outputs Ranges and suggested Voltage Mode settings see D R Properties panel Table 5 9 Power Converter Ranges Type 1 and 3 Power Converters Type 4 Power Converters Suggested Voltage Mode Setting 12 to 12 7 to 7 15V to 17V 15 to 5 15 to 2 15V to 17V 10 to 10 1...

Page 95: ...cts the specified AUX input signal from the front panel Halted Used for linked halt operation between DSA and DSB Static Pulse Used for static operation between DSA and DSB Pulse Generator Selects the pulse generator signal Sequence Flag 1 2 Selects the specified sequence flag Sync 1 2 Selects the specified sync signal CHT1 4 Selects the specified channel test signal Idle Active Idle active flag S...

Page 96: ...ion pull down sets the signal direction Table 5 11 Direction Settings Setting Description A to B Signal sourced by sequencer A and sensed by sequencer B B to A Signal sourced by sequencer B and sensed by sequencer A The relevant VXIplug play API function is tat964_setLtbTriggers Group This command button displays the group configuration panel and is only valid for group enabled front end modules l...

Page 97: ...ve compare level that can be programmed for the selected group This level also establishes the group V voltage level The IO Min valid range is 31 V to 0 V and must be lower than IO Max The group state must be off to update this attribute and all group IO levels are set to 0V The relevant VXIplug play API function is tat964_setGroupMinMax IO Max This numeric entry specifies the maximum drive compar...

Page 98: ...up The over current source valid range is 10mA to 85mA The OC Src attribute is updated immediately when changed The relevant VXIplug play API function is tat964_setGroupAttribute OC Sink This numeric entry specifies the over current sink setting in mA for the selected group The over current sink valid range is 10mA to 85mA The OC Sink attribute is updated immediately when changed The relevant VXIp...

Page 99: ...w 1 4 Window timing signals SEQ_CLK Sequence Clock SEQ_CLK_D Delayed Sequence Clock T0_CLK Pattern Clock Jump Jump signal The relevant VXIplug play API function is tat964_setLocalBusDelay Delay This control is used to specify the delay value for the signal specified by the Delay Signal control The valid delay range is from 0 to 63 and the delay is 0 15 ns step The relevant VXIplug play API functio...

Page 100: ... are more like an open emitter on the VXI backplane The chassis provides 50 ohm termination for these ECLTRG lines which results in a sharp trailing edge In this case programming an active high signal on this panel will drive the backplane signal high This also allows multiple DRMs to actively drive the same trigger line and form a wired OR condition Under certain circumstances it may be desired t...

Page 101: ...Error DRS error flag Pass Valid DRS Pass Valid signal Sequence Reset DRS sequence reset command DRS Sync DRS Sync signal Driver Disable DRS driver disable command Master Reset DRS master reset All DRS coupled sequencers must select the same TTLTRG ECLTRG for the last six listed signals if used These signals are used for DRS signaling The relevant VXIplug play API functions are tat964_setTtlTrigger...

Page 102: ...s always used for these Driver Receiver boards for single ended signals Voltage Mode This pull down control programs the voltage mode for the DR3e DR9 UR14 Driver Receiver boards The selections for this pull down control are Table 5 16 Voltage Mode Settings Setting Description Recommended Usage Mode 0 Selects voltage mode 0 DR3e DR9 UR14 15 V to 17 V For any Power Converter range except for the 0 ...

Page 103: ...rature fault condition Shutdown Low Signal goes low on voltage or temperature fault condition Disabled Signal is not driven MPSIG Signal is assigned to the sequencer MPSIG signal The relevant VXIplug play API function is tat964_setPowerSettings MPSIG Signal This control sets the source of the MPSIG All checked signals are ORed together Table 5 18 MPSIG Source Setting Description Sequence Active MP...

Page 104: ...selections for this pull down control are given along with the recommended error pulse width assuming a 500 MHz master clock Table 5 19 Error Pulse Width Settings Setting Description Typical Usage 2 3 MCLK The error pulse will be from 2 to 3 MCLK periods Recommended for un linked sequencers 3 4 MCLK The error pulse will be from 3 to 4 MCLK periods Recommended for a DRS of size 2 4 DRMs 4 5 MCLK Th...

Page 105: ...ill be set to 0 during the next burst if Step Record Mode is set to either None or Record Count Setting Record Mode to Non Error 0 when Step Record Mode is set to either None or Record Count clears the record memory during the next burst insuring that any previously recorded errors will not persist The relevant VXIplug play API function is tat964_setSequencerRecordMode Config Data Sequencer A B Th...

Page 106: ... ns timing resolution is required no frequency reference Frequency Synthesizer Sequencer timing resolution set to 1 2 FS For example if FS 100 MHz Resolution 1 2 100 000 000 Resolution 5ns 1 ns timing resolution is required an external frequency reference will be used to train the master clock or when a non standard exact data rate is required For example if a 48 MHz data rate is required the synt...

Page 107: ... from another VXI instrument provided across the VXI backplane Pulse Generator System Clock source set to the internal pulse generator signal For test purposes or for when pulse width control of the system clock is required Frequency Synthesizer System Clock source set the to the internal frequency synthesizer signal For the purpose of having a self test The relevant VXIplug play API function is t...

Page 108: ...play API function is tat964_setFreqSynth Synthesizer Ref Source This pull down control programs the frequency synthesizer reference source The selections for this pull down control are Table 5 24 Synthesizer Ref Source Settings Setting Description Internal Reference source set to internal 20 MHz AUX1 AUX12 Reference source set to front panel signal VXICLK10 Reference source set to VXI backplane 10...

Page 109: ...sh within the specified time period The Watchdog Timeout Timer starts when SEQACT begins This timer does not stop during a Pause or Halt including single stepping Generates an event WDTO if the sequence active time exceeds the specified value If the watchdog action is set to Disable Drivers all 32 drivers will tri state when a timeout occurs but any active load or resistive loading remains Sequenc...

Page 110: ...al time timer which can be used in a sequence step that has a Pause In the Sequence Step the Handshake Modifier can be set to the Pattern Timeout The Timer starts when the Pause begins The Pattern Timeout Timer will generate an event when the timer times out The Pause will continue unless the termination condition is subsequently met whereby execution will resume If it doesn t the user can manuall...

Page 111: ...quence Timeout State This toggle control is used to enable disable the sequence timeout feature Table 5 27 Sequence Timeout State Action Setting Description Off Disable sequence timeout bit in event register On Enable sequence timeout bit in event register The relevant VXIplug play API function is tat964_setSequenceTimer Sequence Timeout Time This numeric control is used to specify the sequence ti...

Page 112: ...re Triggers Panel Pause Trigger and Pause Resume Trigger The pause triggers are used to stop the pattern timing during a burst The corresponding resume trigger re starts the pattern timing from where it was stopped A pause resume can be based on the true false state of any of the two pause triggers For example if Pause 1 Trigger was set to AUX1 Low Level and Pause 1 Resume was set to AUX1 High Lev...

Page 113: ...ected jump trigger 1 source is low Trigger This pull down control selects the trigger to program The selections for this pull down control are Table 5 28 Trigger Settings Setting Description Pause Trigger 1 Select Pause Trigger 1 to edit Pause Trigger 1 Resume Select Pause Trigger 1 Resume to edit Pause Trigger 2 Select Pause Trigger 2 to edit Pause Trigger 2 Resume Select Pause Trigger 2 Resume t...

Page 114: ... VXIplug play API functions are tat964_setHandshakePauseTrigger tat964_setHandshakeResumeTrigger tat964_setPhaseResumeTrigger tat964_setJumpTrigger tat964_setHaltTrigger tat964_setExecuteStartTrigger tat964_setExecuteStopTrigger tat964_armIdleSequence tat964_armSequence Test Condition This pull down control programs the trigger test condition The selections for this pull down control are Table 5 3...

Page 115: ...Iplug play API functions are tat964_setHandshakePauseTrigger tat964_setHandshakeResumeTrigger tat964_setPhaseResumeTrigger tat964_setJumpTrigger tat964_setHaltTrigger tat964_setExecuteStartTrigger tat964_setExecuteStopTrigger Edge Test Clear This pull down control programs the trigger event clear The event clear allows the user to program when the rising falling edge flip flops are cleared during ...

Page 116: ...uencer x Pulse Generator where x is the sequencer you wish to configure Figure 5 24 Configure Pulse Generator Each data sequencer has a programmable pulse generator that can be routed to the following signals Data sequencer System Clock VXI TTLTRG VXI ECLTRG Front panel AUX Resolution This toggle control is used to program the pulse generator resolution to either 10 ns or 20 ns The relevant VXIplu...

Page 117: ...ion is tat964_setPulseParameters Step This input control is used to specify the step number when the Mode is set to Single Step The Step is programmed with a range of 0 to 4095 The relevant VXIplug play API function is tat964_setPulseParameters Note This setting is hidden unless the Single Step Mode is selected Period This input control is used to specify the pulse generator period If the resoluti...

Page 118: ...olution is 10 ns the width is programmed in 10 ns steps with a range of 0 to 42 949672950 s If the resolution is 20 ns the width is programmed in 20 ns steps with a range of 0 to 85 8993459 s If the width is equal to or greater than the period in Continuous and Continuous Start mode then the result will be a continuously true pulse If the width plus the delay is greater than the period in Continuo...

Page 119: ...t VXIplug play API function is tat964_setRecordParameters Raw Record Basis This pull down control programs the sequencer raw record basis This control allows the user to select which comparator will be used to determine the data level when the record mode is set to Record Response The selections for this pull down control are Table 5 35 Raw Record Basis Settings Setting Description Good 0 Use good...

Page 120: ...The relevant VXIplug play API function is tat964_setRecordParameters Error Count Basis This pull down control programs the sequencer error count basis This control allows the user to select which error signal to use to determine the error count The selections for this pull down control are Table 5 37 Error Count Basis Settings Setting Description Typical Usage Local Use local error Error counting ...

Page 121: ... DRS Linked error recording is globally enabled Qualified DRS Linked Use BERREN qualified DRS Linked error DRS Linked error recording is enabled per pattern by the BERREN bit qualifier If the Error Address Basis is enabled for DRS or Linked operation then the ERROR signal must be coupled between DRMs Sequencers via the TTL ECL or Linked TRG bus respectively The ECL TRG Bus is recommended for data ...

Page 122: ...t VXIplug play API function is tat964_setDriverEnableControl Pass Fail Basis This pull down control programs the sequencer pass fail basis The control allows the user to select which error signal to use to determine the PASS FAIL state for jumping The selections for this pull down control are Table 5 41 Pass Fail Basis Settings Setting Description Local Use local error Qualified Local Use CONDEN q...

Page 123: ... at least one valid pattern expect code for each pattern in the sequence step If Pass Valid is enabled for a DRS then the Pass Valid signal must be coupled between DRMs via the TTL or ECL TRG bus The ECL TRG Bus is recommended for data rates greater than 10 MHz This is discussed in more detail in the Jumping Halting Counting and Logging Errors section in Chapter 8 The selections for this pull down...

Page 124: ...able control to On will cause the channel or channels which have an over current event to be disabled Setting the Global Disable control to On causes all of the channels on the Driver Receiver board to be disabled whenever any channel has an over current event If Driver Disable is coupled between DRMs via the TTL or ECL Trigger bus or coupled between sequencers on the Linked Trigger Bus then all t...

Page 125: ...et window to cables between 83 3 and 91 3 feet 91 6 99 6 Set window to cables between 91 6 and 99 6 feet 100 108 Set window to cables between 100 and 108 feet 108 3 116 3 Set window to cables between 108 3 and 116 3 feet 116 6 124 6 Set window to cables between 116 6 and 124 6 feet 125 133 Set window to cables between 125 and 133 feet The relevant VXIplug play API function is tat964_setOverCurrent...

Page 126: ...o query which channel caused the drive fault The selections for this pull down control are Table 5 44 Drive Fault Settings Setting Description Disable Disable drive fault signal Enable Enable drive fault signal The relevant VXIplug play API function is tat964_setDriveFaultState Probe This command button displays the Probe panel so the probe parameters can be programmed The probe module connects to...

Page 127: ...t in use See the Jumping Halting Counting and Logging Errors section of Chapter 8 for a discussion on the impact of the Probe Data Setting on data rates The selections for this pull down control are Table 5 45 Probe Data Settings Setting Description Disable The probe data memory is not written to Capture The probe data memory contains comparator and transition results Compare The probe data memory...

Page 128: ...e selected sequence Resume Probe button resumes the paused sequence Both Probe button starts and resumes the sequence The relevant VXIplug play API function is tat964_setProbeConfiguration Probe Button Level This control sets the active level of the probe button Setting options Active Low Active High The relevant VXIplug play API function is tat964_setProbeConfiguration Probe Input Connect This co...

Page 129: ... 5 48 Probe Cal Signal Settings Setting Description AUX2 Calibration signal sourced by AUX2 programmable driver 10V Calibration signal sourced from internal 10V reference 5V Calibration signal sourced from internal 5V reference GND Calibration signal tied to ground 5V Calibration signal sourced from internal 5V reference 10V Calibration signal sourced from internal 10V reference The relevant VXIpl...

Page 130: ...ion screw until the probe module LED labeled D1 illuminates The relevant VXIplug play API function is tat964_probeCalibration DC Cal This control initiates a DC level calibration The user is prompted to connect the probe to the calibration BNC After calibration has been perfomed the user is prompted to update the EEPROM The relevant VXIplug play API function is ...

Page 131: ...on Normal Enable the sequence step pass fail accumulator Default Legacy Disable the sequence step pass fail accumulator Note See the Jumping on and Counting Errors section in Chapter 8 for details on Jump Pass Fail The relevant VXIplug play API function is tat964_setSequencerAttribute Phase 3 Mode This control sets the phase 3 signal mode that selects internal or external operation Internal phase ...

Page 132: ...Resume operation The selections for this pull down control are Table 5 51 Window 3 Mode Settings Setting Description Typical Usage Normal Window 3 is sourced from the internal window generator Default Internally programmed timing for response windows Jump 2 Window 3 is sourced from the Jump 2 trigger signal Externally programmed timing controlled by an external response clock tied to the Jump 2 Tr...

Page 133: ... CH1 and bit 31 corresponds to CH32 CRC Mask A one masks the corresponding channel s capture data Bit 0 corresponds to CH1 and bit 31 corresponds to CH32 The relevant VXIplug play API function is tat964_setSequencerAttribute Static State This pull down control programs the sequencer static state The static state is used to enable or disable the channel static mode setting For sequencer revisions p...

Page 134: ...function is tat964_setStaticState Configuring the I O Channels Configuring the channels is a three step process 1 Select the channels 2 Program channel parameters 3 Configure channel properties Access this panel from the menu bar Config Channels Figure 5 29 Configure Channels Panel Selecting the Channels Before the channel parameters or properties can be programmed the channels must be selected Th...

Page 135: ...p 3 Selects group 3 channels DR4 CH33 through CH48 Channel Parameters The channel parameters consist of Stimulus Signal Stimulus Format Capture Signal Capture Mode Static Mode After any of the channel parameters have been changed the Update command button must be depressed in order for the new channel settings to be programmed Stimulus Signal This pull down control programs the drive phase timing ...

Page 136: ...se Return No action Return Off Phase Assert Output driver goes to level determined by the Pattern Code instruction in Pattern Memory Phase Return Output driver disables Return Zero Phase Assert Output driver goes to level determined by the Pattern Code instruction in Pattern Memory Phase Return Output driver goes to low level Return One Phase Assert Output driver goes to level determined by the Pa...

Page 137: ...igh level immediately after an update Force Off Output driver goes disables immediately after an update Force Phase Phase Assert Output driver goes from high to low level Phase Return Output driver goes from low to high level Output driver coincides with the complement of the phase immediately after an update Force Phase Phase Assert Output driver goes from low to high level Phase Return Output dr...

Page 138: ...bles the channel error test Open Edge Channel error test and data capture performed on the Open edge of the window Close Edge Channel error test and data capture performed on the Close edge of the window Window Channel error test and data capture performed between the Open edge and the Close edge of the window The relevant VXIplug play API function is tat964_setChannelParameters Static Mode This p...

Page 139: ...operties See next section for additional information Configure Channel Properties The channel properties consist of the following nine elements 1 Driver Levels 2 Comparator Levels 3 Driver Slew Rate 4 Output Impedance 5 Over Current Alarm Levels 6 Programmable Load 7 Channel Connect 8 Hybrid Connect 9 Channel Mode These program the properties of the specific Driver Receiver boards that are install...

Page 140: ... The driver levels allow the user to set the Drive High DVH and Drive Low DVL voltage The min max levels are dependent on the installed Driver Receiver board as well as the voltage mode Note The external supply voltages will also need to be adequate for the desired drive levels when using the DR3e with external power option The relevant VXIplug play API function is ...

Page 141: ...cription Fast Sets the DR3e DR9 UR14 slew rate to 1 3 V ns Medium Sets the DR3e DR9 UR14 slew rate to 1 0 V ns Default Sets the DR3e DR9 UR14 slew rate to 0 7 V ns Slow Sets the DR3e DR9 UR14 slew rate to 0 25 V ns Low Power Sets the DR3e DR9 UR14 slew rate to 0 1 V ns Depressing the Custom command button allows the user to specify the DR3e DR9 UR14 Slew Rate Slew Rate and Bias The range for the S...

Page 142: ...s from 0 disable over current monitor to 800 The relevant VXIplug play API function is tat964_setChannelSourceParameters Active Load Depending on the installed Driver Receiver board the user can chose one of several programmable or selectable loads The selections for this pull down control are Table 5 61 Active Load Settings Setting Description None No active load Current Programmable current load...

Page 143: ...to VCOM allows the user to select resistance to the VCOM High level Figure 5 32 Resistive to VCOM Load The selections for this pull down control are Table 5 62 Resistive Settings Setting Description 140 Resistive load set to 140 Ω 151 Resistive load set to 151 Ω 165 Resistive load set to 165 Ω 207 Resistive load set to 207 Ω 240 Resistive load set to 240 Ω 290 Resistive load set to 290 Ω 540 Resis...

Page 144: ...annelConnect Hybrid Connect This control allows the user to connect any of the I O channels to a pin on the front panel called EXTFORCE Note Despite being called EXTFORCE it may be used to drive or sense the channel pin When the hybrid connection is turned On the driver is forced into high impedance and the front panel EXTFORCE pin is connected to the channel There is a series resistance of 40 ohm...

Page 145: ...are grouped as a single channel with the odd channel as the positive and the even channel as negative For example If the channel list is 1 2 5 6 then channel 1 and 2 are grouped and channel 5 and 6 are grouped as follows CH1 Diff CH1 CH2 Diff CH1 CH5 Diff CH3 CH6 Diff CH3 If no other differential groups are assigned then CH3 Single ended CH3 CH4 Single ended CH4 CH7 Single ended CH7 The relevant V...

Page 146: ...ct A This allows the user to set the over current threshold of the selected channel group The detect level can be set from 0 0 A to 1 A in increments of 62 5 mA The relevant VXIplug play API function is tat964_setUtilitySourceParameter All Channels Sets the compare input and OC detect levels of all four channel groups to the current panel settings The relevant VXIplug play API functions are tat964...

Page 147: ...t Systems Figure 5 34 Configure AUX Channels Panel Figure 5 35 Configure AUX Channels Panel UR14 The AUX channels are a set of 12 multi purpose signals that can be used for any of the following I O resources 1 Trigger Source Input 2 Frequency Synthesizer Reference Clock Input 3 System Clock Input ...

Page 148: ...Sequence Flag d Pass Fail e Error 11 Numerous Factory Test Outputs Table 5 64 DRn AUX Configuration Driver Receiver Board AUX1 AUX4 AUX5 AUX8 AUX9 AUX12 DR1 LVTTL LVTTL ECL DR2 LVDS LVTTL ECL DR3E Programmable LVTTL ECL DR4 TTL TTL Not Installed DR7 RS422 485 LVTTL ECL DR8 TTL TTL ECL DR9 Not installed LVTTL Not Installed Table 5 65 UR14 AUX Configuration Signal Logic Special Use AUX1 A AUX2 A Pro...

Page 149: ...tial or bipolar Shares front panel pin with AUX7 A AUX12 A ECL differential or bipolar Shares front panel pin with AUX8 A AUX1 B AUX4 B Programmable General purpose AUX5 B AUX8 B LVTTL Bipolar ECL selectable General purpose AUX9 B AUX12 B ECL differential or bipolar General purpose Configuring the AUX UAUX Signals Configuring the AUX UAUX signal is done by double clicking the left mouse button on ...

Page 150: ...UX Source Settings Setting Description Phase 1 4 Phase timing signal Window 1 4 Window timing signal Waveform 1 4 Waveform signal Sync 1 2 Sync signal Idle Active 1 Active 0 Not Active Sequence Active 1 Active 0 Not Active Channel good 1 Channel good 1 comparator signal Channel good 0 Channel good 0 comparator signal Waveform 5 Waveform 5 signal Waveform 6 Waveform 6 signal Input Bus Select 1 4 In...

Page 151: ...tine Return RTN Return Flag LSTSEQ Last Sequence Jump Test 1 4 Test signal The Channel Good 1 Channel Good 0 selections can select any of the front end channels using the tat964_setAuxChannelSelect API The Input Bus Select selections can select any of the AUX TTL or ECL trigger Local Trigger Bus or Channel Test 1 using the tat964_setAuxInputBusSelect API The relevant VXIplug play API function is t...

Page 152: ...isplays the panel to allow the user to configure the Programmable AUX Driver Receiver settings Refer to Configure Channel Properties earlier in this chapter for control descriptions for this panel The relevant VXIplug play API functions are tat964_setAuxSourceLevels tat964_setAuxSourceParameters tat964_setAuxSlewRate tat964_setAuxSenseLevels tat964_setAuxSenseParameters tat964_setAuxLoadState ECL ...

Page 153: ...able that allows it to pass the event to the interrupt logic on the digital board The five hardware groups are 1 Data Sequencer A Enables set in the Execute DSA View Sequence Events panel 2 Data Sequencer B Enables set in the Execute DSB View Sequence Events panel 3 Driver Receiver Board A Enables set in the Execute DSA View Driver Receiver Events panel 4 Driver Receiver Board B Enables set in the...

Page 154: ...XI interrupt to be generated when any of the associated hardware groups enabled event bits goes from false to true The relevant VXIplug play API function is tat964_setInterruptMode Event False This control enables a VXI interrupt to be generated when any of the associated hardware groups enabled event bits goes from true to false The relevant VXIplug play API function is tat964_setInterruptMode Ev...

Page 155: ...to control the channel drivers and receivers Each timing set has either one or four phase window groups based on the programmed timing mode Phases control the driver operation and consist of an Assert and a Return The Assert signal loads the next pattern code in to the output driver Pattern codes are discussed in the next section The Return signal is used to enable the format code in the driver Th...

Page 156: ...utput level Access this panel from the menu bar Edit Data Sequencer x Timing Sets Where x is the sequencer you wish to configure Figure 5 40 Data Sequencer Timing Sets Panel To program a timing set scroll down the list until the desired timing set number is visible Timing set numbers are assigned based on the current timing mode Per Step Multi 1024 timing sets with four phase window groups per tim...

Page 157: ... zero For example Phase 1 and Window 1 are disabled during TS2 in the configuration shown below The relevant VXIplug play API function is tat964_setTimingSetData Timing Set Value Rules For valid timing signal operation the following rules must be followed Phase pulse width must be greater than seven i e the Return value must be at least eight more than the Assert value Window pulse width must be g...

Page 158: ...eturn 100 Pattern 3 TS3 Assert 0 Return 75 Idle Standby Timing One of the unique features of the DRM is the Idle Standby state After the execution of a sequence burst the sequencer will enter the Idle Standby state The user can define the Idle Standby state timing and pattern such that UUT stimulus can be maintained between pattern bursts A single pattern can be specified so that the pattern memor...

Page 159: ...ed pattern sets The associated step number size and offset are displayed The size of a pattern set can be from 1 to 262144 The offset can be from 0 to 262140 and must be a multiple of four The relevant VXIplug play API functions are tat964_queryPatternSet tat964_queryPatternSetList Append This control allows the user to append more patterns to the selected pattern set ...

Page 160: ...peats the previous code The driver allows pattern set overlaps when appending patterns If you don t want pattern sets to overlap make sure there s enough space for the appended patterns This can be facilitated by assigning the pattern offset initially see Assign function next Press the Close command button to exit the panel without any changes The relevant VXIplug play API function is tat964_appen...

Page 161: ...ly command button Assigned pattern memory will not be initialized Press the Close command button to exit the panel without any changes The relevant VXIplug play API function is tat964_assignPatternSet Edit Data This control displays the view edit pattern set panel This panel allows the user to view edit the contents of the pattern set memory Double clicking on the desired pattern set can also open...

Page 162: ...t Sequencer Data Panel Each column contains the TEST code PROBE code and the pattern codes for all the channels The pattern codes are described in Figure 5 47 and Table 5 TTT The pattern set is displayed in pages of 32 patterns The View menu bar lists the page control shortcuts listed below Figure 5 45 Pattern Set Data View Menu ...

Page 163: ...legend of all the available TEST and CH entries Figure 5 47 Pattern Codes The row labeled TEST displays the test code for each pattern There are two test flags per pattern 1 BERREN Burst Error Enable This flag allows the user to designate which patterns will be examined for Burst Error Burst Error counting and the logging of errors in the Error Address Memory 2 CONDEN Condition Enable This flag al...

Page 164: ...38 Rev K Model T940 User Manual Astronics Test Systems Soft Front Panel Operation 5 83 The row labeled PROBE displays the probe expect code for each pattern There are thirty four probe expect codes Figure 5 48 Probe Codes ...

Page 165: ...sses the RH two or more times and ends between RL and RH 51 HPL i Signal starts above RH crosses RL and RH three or more times and ends below RL F9 HPM j Signal starts above RH crosses RH three or more times RL two or more times and ends between RL and RH F1 HGFE k Signal starts above RH crosses the RH three or more times crosses RL once and ends below RL D9 L l Signal remains below RL 0A LG m Sig...

Page 166: ...etween RL and RH crosses the RH two or more times and ends between RL and RH 50 MLG 1 Signal starts between RL and RH crosses the RL two or more times and ends between RL and RH A0 MPH 2 Signal starts between RL and RH crosses RL two or more times RH three or more times and ends above RH F4 MPL 3 Signal starts between RL and RH crosses RL three or more times RH two or more times and ends below RL ...

Page 167: ...er to Invert Code column of this table Expect Valid Low L Off X CVL Expect Valid High H Expect Valid High H Off X CVH Expect Valid Low L Expect Valid V Off X CVL or CVH Expect Between B Expect Between B Off X CVL and CVH Expect Valid V Drive Low Expect Low l On DVL CVL Drive High Expect High h Drive High Expect High h On DVH CVH Drive Low Expect Low l Drive Low Expect High On DVL CVH Drive High Ex...

Page 168: ...e the first line of the file Header Format The format of the header is TAT964 PAT DUMP dd nnnnnn where dd is the format 00 Pattern Data ASCII Hex 01 Pattern Data Binary 02 Pattern Data ASCII String 03 Pattern Data Flags and Probe Expect ASCII Hex 04 Pattern Data Flags and Probe Expect Binary 05 Pattern Data Flags and Probe Expect ASCII String nnnnnn is the number of patterns Data Format The data f...

Page 169: ... 88 Astronics Test Systems Table 5 73 ASCII Binary Data Format Pattern Code ASCII Binary Value Z 0 C 1 0 2 1 3 R 6 I 7 L 8 H C V D B 9 l A h F E B Flag Code Bit15 Bit 14 Code a 3 b 2 c 1 n 0 Probe Expect Bit 13 through Bit 8 a 0 b 1 c 2 y 18 z 19 0 1A 1 1B 2 1C 3 1D 4 1E 5 1F 6 20 ...

Page 170: ...le above all channels are set to Z except channel 1 is set to 0 in pattern one In pattern two all channels are set to Z except channel 16 is set to 1 Binary The binary format represents the pattern data as raw binary data The pattern data is stored in four sequential 32 bit blocks five if flags and probe expect are included The block order is listed below Table 5 74 Binary Block Format Block Numbe...

Page 171: ...b Channel 1 enabling the CRC C Channel 2 through channel 32 repeating the previous state R Probe expect low middle n Editing Waveforms Up to four waveforms can be defined and output during a pattern for generating UUT handshake or clock stimulus The first four waveforms are enabled per sequence step and they replace certain Phase Window signals as mapped below Waveform 1 Mapped to Phase 4 Waveform...

Page 172: ...est Systems Soft Front Panel Operation 5 91 Where x is the sequencer you wish to configure Figure 5 50 Edit Waveforms Panel Waveform 1 Figure 5 51 Edit Waveforms Panel Waveform 5 Table Size This pull down control programs the waveform table size for waveforms 1 4 ...

Page 173: ... VXIplug play API function is tat964_setWaveformTableSize Waveform This pull down control selects the waveform to view edit Table Number This control selects the table number to view edit Waveforms five and six only have one table Waveform Definition This control allows the user to define the waveform Specifying the beginning level and the bit number of subsequent transitions defines the waveform ...

Page 174: ...e Parameters The sequence parameters consist of the following entries 1 Loop Counter Mode 2 Pipeline Mask 3 Strobe Vector Bit Table Selection 4 Channel Test Access this panel from the menu bar Edit Data Sequencer x Sequence Parameters Where x is the sequencer you wish to configure Figure 5 52 Data Sequencer Parameters Panel LC0 LC15 These controls program the loop counter mode There are sixteen 16...

Page 175: ... result by the corresponding depth of the pipeline in patterns See the Jumping Halting Counting and Logging Errors section in Chapter 8 for a more in depth explanation of how pipelining affects jumping counting burst errors and the logging of errors in the error Address Memory The relevant VXIplug play API function is tat964_setConditionPipelineMask Vector Strobe This control allows the user to se...

Page 176: ...ction can be programmed for the selected sequencer The four vector signals comprise an index into a vector jump table that specifies the jump address as well as the timing set indexed timing mode only The vector table signals are only used if the vector jump bit is set during a sequence jump step Configuring the vector signals consists of the following 1 Select the Source 2 Program the Input Mode ...

Page 177: ...e Table 5 78 Vector Bit Input Mode Settings Setting Description Normal Do not modify input signal before testing Inverted Invert input signal before testing The relevant VXIplug play API function is tat964_setVectorJumpSignal Set Vector Table This command button displays the Edit Vector Table panel so the vector table settings can be programmed for the selected sequencer The vector table is indexe...

Page 178: ...function is tat964_setVectorJumpTable Timing Set When the timing mode is set to indexed this control allows the user to specify the timing set for the current vector jump index The relevant VXIplug play API function is tat964_setVectorJumpTable Set Channel Test This command button displays the Edit Channel Test panel so the channel test settings can be programmed for the selected sequencer Configu...

Page 179: ...represents a valid high test and a zero represents a valid low test The relevant VXIplug play API function is tat964_setSequenceChannelTest Mask This allows the user to enter the mask value for the channel test signal Bit 0 of the mask value maps to the lowest channel of this sequencer and Bit 31 maps to the highest channel and this is the case for both A and B sequencers A one disables the compar...

Page 180: ...to 4096 sequence steps are available for Indexed and Per Step Single timing modes Up to 1024 sequence steps are available for Per Step Multi timing mode The Delete key will clear the step data contents de allocate any assigned pattern data and initialize the step settings A double click on any of the step number cells opens a Sequence Step Data panel for that cell The T964 Sequencer Operation Deta...

Page 181: ...f the master clock is set to 500 MHz then a setting of 20 would result in a system clock period of 20 ns 20 1 2 2 ns 20 ns With a master clock of 100 MHz the system clock period would be 100ns 20 1 2 10 ns 100 ns The valid values for T0CLK are from 20 to 65550 The relevant VXIplug play API function is tat964_setSequenceClock Clocks per Pattern This numeric control defines the Clocks per Pattern CP...

Page 182: ... span cannot exceed the System Clock period If a Phase is triggered by the Pattern Clock and the CPP 1 then that Phase can span the Pattern Clock period Windows are only triggered on the Pattern Clock and can span the Pattern Clock period while still observing the Timing Set Value Rules Timing Set This numeric control sets the timing set number for the sequence step This control is only visible wh...

Page 183: ...routine The relevant VXIplug play API function is tat964_setSequenceGosubReturn Sequence Flag 1 and Sequence Flag 2 This control allows the user to specify the level of Sequence Flag 1 and Sequence Flag 2 during this step These general purpose outputs can be routed any of the AUX outputs as well as the VXI TTLTRG and ECLTRG outputs The relevant VXIplug play API function is tat964_setSequenceFlags ...

Page 184: ...only visible if the jump type is set to Normal or Gosub If the jump condition is true then the next step number will be the value specified by the Jump Step instead of the next sequential step number The jump action takes precedence over the Last Step flag The relevant VXIplug play API function is tat964_setSequenceJump Jump Condition This pull down control programs the Jump Type Mode This control...

Page 185: ...r 4 not true The true false state of the jump triggers is based on the jump trigger test condition If the jump trigger test condition is set to Low Level then True would indicate the jump trigger signal is low and not True would indicate the jump trigger signal is high Note Any CONDEN enabled FAIL during the Sequence Step will prevent a PASS See the Jumping Halting Counting and Logging Errors sect...

Page 186: ...er to jump to is specified by the Jump Step control This control is only visible if the jump type is set to Normal or Gosub The relevant VXIplug play API function is tat964_setSequenceJump Pass Fail Clear This control programs the Pass Fail Clear Mode during this step The T940 pass fail flag is used for conditional jumping and indicates the results of a channel compare pattern code The pass fail f...

Page 187: ...ence burst The Record Memory contains either the error flag or response data for the previous sequence burst The selections for this pull down control are Table 5 81 Step Record Mode Settings Setting Description None Error counting and all three record memories are disabled Record Count Error Counting enabled Record Error Error counting and all three memories are enabled and the Record Memory is s...

Page 188: ...Set panel This panel allows the user to assign a block of pattern memory to the current sequence step The Number of Patterns control specifies how many patterns will be assigned and initialized to the current sequence step The Memory Offset control specifies the location of the first pattern If the offset is set to 1 the driver automatically increments the offset to the next higher multiple of 4 f...

Page 189: ...ems Figure 5 59 Initialize Step Pattern Set Panel The relevant VXIplug play API function is tat964_initPatternSet If the Patterns control reads a number greater than zero then this command button displays the Edit Pattern Data panel see Editing the Patterns in Chapter 5 Figure 5 60 Edit Pattern Set Panel ...

Page 190: ...rol allows the user to assign a signal Pause that can be either internal or external which will pause the sequencer When paused the following will stop Phases Windows Waveforms For each pause signal selection there is a corresponding signal that will continue Resume sequence operation See the Pause and Halt section of Chapter 8 for additional details about the use of pause Pause Signal This pull d...

Page 191: ... Resume Trigger Phase 4 Return Phase 4 Return edge occurs Phase 4 Resume Trigger The true false state of the pause triggers is based on the pause trigger test condition If the pause trigger test condition is set to Low Level then true would indicate the pause trigger signal is low and false would indicate the pause trigger signal is high Note The Resume Signal selection is covered in the Configure...

Page 192: ...dedicated and do not need to be enabled Waveform1 Waveform4 This control allows the user to enable disable the specific waveform number The relevant VXIplug play API function is tat964_setSequenceWaveform Waveform Table This numeric control allows the user to program the waveform table for the sequence step Numeric values can range from Waveform Tables 1 through 16 The relevant VXIplug play API fu...

Page 193: ...equence Sequence execution and control is performed from the Execute panel Access this panel from the menu bar Execute DSx Where x is the sequencer you wish to execute Figure 5 62 Executing a Sequence Panel The following sections describe the execution overview as well as the indicators and controls of the execute panel ...

Page 194: ...iption Setting Description Entry Condition RESET 1 Idle Active false 2 Sequence Active false 3 Halt flag false 4 Paused flag false 5 Active step 0 6 Pattern Memory Free pon reset STANDBY 1 Idle Active false 2 Sequence Active false 3 Halt flag false 4 Paused flag false last step stop standby finish mode RESET last step stop standby finish mode IDLE STANDBY ACTIVE HALT PAUSE pon reset execute execut...

Page 195: ...equence Active true 3 Halt flag true 4 Paused flag false 5 Active step User 6 Pattern Memory Free halt PAUSE 1 Idle Active false 2 Sequence Active true 3 Halt flag false 4 Paused flag true 5 Active step User 6 Pattern Memory Busy pause The following table describes the state transitions and the execute panel control to perform it Table 5 85 Execute State Transition Description Transition Descripti...

Page 196: ...alt Halt the active sequence Make sure the Halt Mode is not set to Disabled Depress the Halt command button If sequence was active Halt LED should be red halted If sequence was not running Halt LED should be green armed resume single step Halt resume or single step While in HALT state Depress Resume command button to resume Depress Halt command button to single step pause Pause the primary sequenc...

Page 197: ... one or more burst errors have occurred in the previous sequence run The relevant VXIplug play API function is tat964_queryErrorFlags Errors This numeric indicator displays the number of pattern errors from the previous sequence burst The relevant VXIplug play API function is tat964_queryErrorFlags Power Converter Alert Illuminated red indicates that one or more fault bits are set in the Power Con...

Page 198: ...ddress This numeric indicator displays the current pattern address The relevant VXIplug play API function is tat964_querySequencerStatus Record Count This numeric indicator displays the current record count The relevant VXIplug play API function is tat964_queryRecordCount Timing Set This numeric indicator displays the current timing set index only visible in indexed timing mode The relevant VXIplu...

Page 199: ... drive fault event if enabled to do so A channel over voltage event for Driver Receiver modules employing this feature The relevant VXIplug play API function is tat964_setDriverEnable V V This control allows power to be applied to those D R boards which require power It also enables the isolation relays to be closed if they re designated to be closed by the Connect State Note The following Driver ...

Page 200: ...t mode determines where execution will halt following either a manual halt Halt command button or an external halt trigger See the Jumping Halting Counting and Logging Errors section in Chapter 8 for additional details about the use of halt The selections for this pull down control are Table 5 87 Halt Mode Settings Setting Description Disable Halt signal ignored Pattern Halt the current sequence a...

Page 201: ... relevant VXIplug play API function is tat964_setHaltMode Finish Mode This pull down control programs the finish mode When a sequence execution completes the sequencer will enter either the Standby or Idle state The Standby state outputs the first pattern of the specified step and pattern memory can be accessed by the user while the sequencer is in Standby The Idle state outputs the entire pattern...

Page 202: ...d jump End of Sequence The stop signal causes the current sequence burst to terminate at the end of the sequence of a continuous or looped burst The relevant VXIplug play API function is tat964_setStopMode CRC Type This pull down control programs the CRC type for the next burst The selections for this pull down control are Table 5 90 CRC Type Settings Setting Description CRC16 CRCs generated in th...

Page 203: ...r This control selects which sync pulse signal to program either Sync 1 or Sync 2 Event and Step This pull down control programs the sync event The sync pulse event can be set to either the start of a sequence or a specific step The selections for this pull down control are Table 5 91 Finish Mode Settings Setting Description Start The sync pulse begins from the start of the sequence Step The sync ...

Page 204: ... is not the Primary Sequencer in a DRS The relevant VXIplug play API functions are tat964_executeIdleSequence tat964_armIdleSequence Execute If the Start Arm control is set to Start this command button starts the sequence at the sequence step specified in the Execute Step control If the Start Arm control is set to Arm this command button arms the sequence at the step specified in the Execute Step ...

Page 205: ... The relevant VXIplug play API function is tat964_stopSequence Reset The Reset command button forces the sequence to the reset state Sequence Step 0 with the Channel Drivers setting unchanged The relevant VXIplug play API function is tat964_resetSequence Master Reset The Master Reset command button forces the sequence to the reset state Sequence Step 0 and also sets the Channel Drivers to Disabled...

Page 206: ...ed input data is valid and if it matches the expected results The Burst Error LED and Errors are result indicators located on the execution panel Additional result data can be accessed from the Execute DSx menu bar View selection Where x is the sequencer you wish to query Figure 5 65 Execute DSA View Menu These panels allow the user to query the recorded memory results and status indicators from t...

Page 207: ...e that specifies the response delay from 0 to 6 5ms Stimulus delay is no longer supported Stimulus Delay This control sets the delay from the start of a sequence execution to when the stimulus pattern will be output and is only available in sequencer revisions prior to 0 21 The delay can be set from 20ns to 40s with 10ns resolution Note The Stimulus Delay must be less than the Response Delay The r...

Page 208: ...state The selections for the table column pull down control are Table 5 92 Static Stimulus Settings Setting Description Z Disable the channel 0 Drive to low level 1 Drive to high level X Uninstalled channel The relevant VXIplug play API function is tat964_setStaticData Response This table column contains the stimulus input state of the previous static execution The selections for the table column ...

Page 209: ... pattern code that is not Invert Previous Code or Repeat Previous Code Note The Kept Data is updated at the end of a pattern so the contents of the kept data when halted or paused will contain the codes from the previous pattern The relevant VXIplug play API function is tat964_queryKeptPattern Results The Results data display is accessed from the Execute DSx View Results menu bar selection Where x...

Page 210: ...or address data from the previous sequence execution Record Index Display the error address data from the previous sequence execution Record Data Display the error address data from the previous sequence execution Probe Data Display the error address data from the previous sequence execution Save Results This command button will display a file save panel that allows the user to select and existing...

Page 211: ...er of the error offset Pattern number pma Pattern Memory Address data Record memory Record Index Save File Format The Record Index results are saved in the following format header line feed step offset line feed Where header STEP OFFSET step Step number of the error offset Record memory offset where the results are saved Record Data Save File Format The Record Data results are saved in the followi...

Page 212: ...Step number of the error offset Pattern number data Probe Memory contents CRCs Display The CRC memory display is accessed from the Execute DSx View Results menu bar selection and setting the View control to CRCs Where x is the sequencer you wish to query Figure 5 69 View CRC Panel CRCs can be accumulated for all 32 channels as well as AUX1 which is dedicated for the probe channel shown at the left...

Page 213: ...errors of a sequence execution and is displayed in the Step and Addr columns The Pattern column is calculated based on the Record Type setting and Record column is read from the record memory The relevant VXIplug play API function for Step and Addr data is tat964_queryErrorAddress The relevant VXIplug play API function for Record data is tat964_queryRecordData The relevant VXIplug play API functio...

Page 214: ...te DSx View Results menu bar selection and setting the View control to Record Index Where x is the sequencer you wish to query The record index memory stores the sequence step and pattern index of the first 1024 steps of a sequence execution When the record type is set to indexed the sequence results are stored sequentially in the record memory starting at offset 0 The record index memory allows t...

Page 215: ...ystems Figure 5 73 Record Index Panel The relevant VXIplug play API function is tat964_queryRecordIndex Record Data Display The record memory display is accessed from the Execute DSx View Results menu bar selection and setting the View control to Record Data Where x is the sequencer you wish to query ...

Page 216: ...n error will be registered If an error is not registered it means that the channel for this pattern was not only as expected but also that there was a valid capture If an error is registered it could mean that the channel for this pattern was either not as expected or there was a capture fault Capture faults are registered separately so that one can determine if there was a capture fault for this ...

Page 217: ... window 4 open 1 Good 0 level at window 4 open 2 Good 1 level at window 4 close 3 Good 0 level at window 4 close 4 Positive transition at good 1 level 5 Positive transition at good 0 level 6 Negative transition at good 1 level 7 Negative transition at good 0 level The combination of the eight bits allows the following probe states Middle Signal remains between RL and RH High Signal remains above R...

Page 218: ...e RH crosses the RH two or more times and ends above RH Rising Edge Glitch Middle Signal starts below RL crosses RL once crosses RH two or more times and ends between RL and RH Rising Edge Glitch Signal starts below RL crosses RL once crosses RH three or more times and ends above RH Middle Low Signal starts between RL and RH crosses the RL once and ends below RL Middle Low Glitch Signal starts bet...

Page 219: ...starts above RH crosses RH once crosses RL two or more times and ends between RL and RH Falling Edge Glitch Signal starts above RH crosses RH once crosses RL three or more times and ends below RL Middle Pulse Middle Signal starts between RL and RH crosses RH and RL two or more times and ends between RL and RH High Pulse Middle Signal starts above RH crosses RH three or more times RL two or more ti...

Page 220: ...mes and ends below RL The relevant VXIplug play API function is tat964_queryProbeData Status Indicator Panels The status indicator panels allow the operator to view the available status results to determine if the previous execution sequence is valid The following panels are available Sequencer Events Sequencer Data Driver Receiver Events Driver Receiver Data VXI Trigger Readback Power Query Power...

Page 221: ...encer enable condition and event bits are defined Table 5 96 Sequence Enable Condition Event Bit Descriptions Bit Name Description 0 Idle Started The idle state has been entered 1 Sequence Started The sequence active state has been entered 2 External Halt One or more external halts occurred 3 Burst Error One or more errors occurred 4 Jump One or more jumps occurred ...

Page 222: ...n already in one 17 Return Subroutine Error Return encountered when not in a subroutine 18 Subroutine Active Error Sequence completed while still in a subroutine 19 Idle Complete Idle sequence completed 20 Sequence Complete Sequence completed 21 External T0_CLK Error The external T0_CLK is too fast or glitchy The edges which cause the too fast condition are ignored such that the resultant T0_CLK p...

Page 223: ...interrupt event The relevant VXIplug play API function is tat964_setEventEnable Condition These LEDs indicate the current state of the associated signal The relevant VXIplug play API function is tat964_querySequencerCondition Event These LEDs indicate if the state of the associated signal went true The relevant VXIplug play API function is tat964_querySequencerEvent Clear Event This command button...

Page 224: ...PI function is tat964_querySequencerCounterStatus Record Index Count This indicator displays the number of valid entries in the record index memory The relevant VXIplug play API function is tat964_querySequencerRecordIndex Sync Error Step This indicator displays the step number that was active when the DRS sync error occurred The relevant VXIplug play API function is tat964_querySequencerSyncError...

Page 225: ...s Bit Descriptions Bit Name Description 0 PAUSED Sequencer is paused 1 ICLKOK 500 MHz Clock OK 2 IDDCM Input Delay DCM locked 3 ISPEND Internal Stop Pending 4 ESPEND External Stop Pending 5 ISTART Internal Start Pending 6 ESTART External Start Pending 7 HALT Sequencer is Halted 8 STEP Single Step Pending 9 IACT Idle Sequence Active 10 SACT Sequence Active 11 DEN Drivers Enabled 12 EHALT External H...

Page 226: ... 84 V High V too high error 29 00 29 70 V High V too high error 2 80 2 91 V Low V too low error 19 50 19 8 Delta Fault The V to V delta error 34 00 34 3 Ground Fault DUT_GND to SIG GND delta error greater than 390 mV even if it s not being used as the DUT_GND for the Pin Electronics devices 0 39 0 39 Temperature Alert One or more of the Pin Electronics devices has exceeded the specified temperatur...

Page 227: ...36 0 Group 2 Delta Fault Group 2 V to V delta too large 36 0 Group 3 Delta Fault Group 3 V to V delta too large 36 0 VTM1 Fault Power converter VTM1 fault set NA VTM2 Fault Power converter VTM2 fault set NA VTM3 Fault Power converter VTM3 fault set NA 24V Fault The 24 V fuse reports open NA 12V Fault The 12 V fuse reports open NA 24V Fault The 24 V fuse reports open NA 12V Fault The 12 V fuse repo...

Page 228: ...t VXIplug play API function is tat964_setEventEnable Condition These LEDs indicate the current state of the associated signal The relevant VXIplug play API function is tat964_queryFrontEndCondition Event These LEDs indicate if the state of the associated signal went true The relevant VXIplug play API function is tat964_queryFrontEndEvent Clear Event This command button resets the event LEDs Note A...

Page 229: ...7 CH17 CH18 CH9 CH10 NU 8 CH1 CH2 CH15 CH16 NU 9 CH7 CH8 CH12 NU 10 CH31 CH32 CH13 NU 11 CH27 CH28 CH14 NU 12 AUX3 AUX4 CH11 NU 13 D2 Local D2 Local NU 14 CH19 CH20 CH17 CH18 NU 15 CH21 CH22 CH23 CH24 NU 16 CH5 CH6 CH20 NU 17 CH11 CH12 CH21 NU 18 CH15 CH16 CH22 NU 19 CH29 CH30 CH19 NU 20 D3 Local D3 Local NU The relevant VXIplug play API function is tat964_queryFrontEndAlert Driver Receiver Data P...

Page 230: ... comparator CVH Drive Fault A 1 LED illuminated indicates that the channel has triggered a drive fault event Over Current A 1 LED illuminated indicates that the channel has triggered an over current event Capture Fault A 1 LED illuminated indicates that the channel has triggered a Capture Fault AUX A 1 LED illuminated indicates that the channel is currently higher than the high comparator The DR3e...

Page 231: ...bar selection Where x is the sequencer you wish to query Figure 5 81 VXI Trigger Readback Panel This panel displays the current level of the eight TTL and two ECL VXI backplane triggers The LED illuminated indicates a high state Note A high TTLTRG signal is active low on the backplane The relevant VXIplug play API function is tat964_queryVxiTrigger Query Power Results Message The query power resul...

Page 232: ...relevant VXIplug play API function is tat964_queryPowerOverhead Power Converter Condition Panel The power converter conditions display is accessed from the Execute DSx View Power Converter Condition menu bar selection There is only one power converter per DRM so the DSA and DSB selection will display the same panel Figure 5 83 Power Converter Condition Panel The following power converter bits are ...

Page 233: ... Fault High current condition detected Over Current Fault Over current condition detected and shut down the power converter The relevant VXIplug play API function is tat964_queryPowerConverterCondition Counter Timer Panel The Counter Timer Panel is accessed from the Execute DSx View Counter Timer menu bar selection where x is sequencer A or B One Counter Timer is provided for each sequencer Figure...

Page 234: ... Initiate command button performs a time interval measurement from the rising edge input 1 to the falling edge of input 1 Negative Pulse Initiate command button performs a time interval measurement from the falling edge input 1 to the rising edge of input 1 The relevant VXIplug play API function is tat964_setCounterFunction tat964_queryCounterFunction Input 1 3 Source These controls allow the coun...

Page 235: ...control sets the gate aperture time for the frequency period and timed totalize functions Table 5 104 Counter Timer Aperture Setting Description 1us One microsecond gate time 10us Ten microsecond gate time 100us One hundred microsecond gate time 1ms One millisecond gate time 10ms Ten millisecond gate time 100ms One hundred millisecond gate time 1s One second gate time 10s Ten second gate time The ...

Page 236: ...Performs one measurement with initiate The relevant VXIplug play API function is tat964_setCounterTrigger tat964_queryCounterTrigger Initiate Generates an immediate trigger to the timer counter The relevant VXIplug play API function is tat964_CounterInitiateTrigger Results Retrieve the results of the selected counter timer function The relevant VXIplug play API function is tat964_measureCounterRes...

Page 237: ...est functions Calibration Firmware Updates Temperature Monitoring Voltage Monitoring The instrument functions are dependent on the Driver Receiver boards installed For example the DR1 Driver Receiver board does not require voltage calibration and does not contain voltage and temperature monitoring hardware Self Test The self test function is accessed from the Instrument Self Test menu bar selectio...

Page 238: ...CH16 RAM test failed 16 DSA pattern 2 CH17 CH24 RAM test failed 17 DSA pattern 3 CH25 CH32 RAM test failed 18 DSA record RAM test failed 19 DSA probe flag RAM test failed 20 DSB 500 MHz clock test failed 21 DSB frequency synthesizer test failed 22 DSB VXICLK10 test failed 23 DSB pulse generator test failed 24 reserved 25 reserved 26 reserved 27 DSB sequence RAM test failed 28 DSB timing set RAM te...

Page 239: ...M test function saves the current memory contents and performs a full RAM test on all the internal memories The full RAM test performs multiple read write cycles to each RAM at every address location The full RAM test utilizes special hardware to test the pattern record and probe memories at speed The relevant VXIplug play API function is tat964_ramTest Power Converter Test The power converter tes...

Page 240: ...lds Power Converter Mode V Min V Max V Min V Max 12 to 12 15 520 16 480 16 068 15 132 15 to 5 9 312 9 888 19 776 18 624 10 to 10 15 520 16 480 14 523 13 677 2 to 7 11 640 12 360 9 888 9 312 5 to 15 18 624 19 776 9 888 9 312 0 to 24 27 936 29 664 4 635 4 365 2 to 22 25 608 27 192 6 180 5 820 The relevant VXIplug play API functions are tat964_setPowerConverter tat964_setPowerConverterState tat964_qu...

Page 241: ...be lost Figure 5 89 Calibration Confirmation Panel Selecting Yes displays the main calibration panel If the installed Driver Receiver board requires calibration the Calibrate Function control will list the available calibration items Not all Driver Receiver boards require calibration Figure 5 90 Calibration Panel Driver Receiver This control selects which Driver Receiver board to calibrate Calibra...

Page 242: ...d low level calibration ISource ISink Selects the source and sink current calibration IAL IAH Selects the current alarm high and low level calibration ADC Reference Selects the ADC reference voltage calibration Source Sink Load Selects the source sink load resistance calibration Delete Calibration Used to delete section two data Serial Number This control displays the Driver Receiver board serial ...

Page 243: ... 91 Confirm Calibrate Panel Note Pin electronic calibration data is stored for each voltage mode 15 V to 17 V and 7 V to 24 V Calibration should be performed with the power converter setting that will be used for testing for each voltage mode Figure 5 92 Calibrate Warm up Panel The selected calibration procedures will begin when the temperature reaches 80º C or the Continue command button is press...

Page 244: ...s Figure 5 93 Calibrate Run Panel The relevant VXIplug play API functions are tat964_calibrateChannel tat964_setRefOutput tat964_setRefVoltage tat964_setForceConnect tat964_setForceLoad tat964_setRefLoad Verify This command button executes the selected calibrate function verify routine The SFP will prompt the operator to confirm the action and then apply power to the Driver Receiver board ...

Page 245: ...will be prompted to select the directory where the verification report will be created and saved Figure 5 95 Verify Select Directory Panel Note Pin electronic calibration data is stored for each voltage mode 15 V to 17 V and 7 V to 24 V Verification should be performed with the power converter setting that was used for calibration for each voltage mode ...

Page 246: ...e reaches 80º C or the Continue command button is pressed The unit should be verified at its normal application temperature Refer to the Calibration Temperature section in Chapter 6 for more information Once verification has begun progress data is displayed in the Status control Figure 5 97 Verify Run Panel The relevant VXIplug play API functions are tat964_verifyChannelCalibration ...

Page 247: ...his command button writes the new calibration data to non volatile memory The relevant VXIplug play API function is tat964_updateCalibrationData Monitor Temperature Panel This panel shows the temperature of the following components within the DRM Digital Board Sequencer FPGAs DR3e DR9 and UR14 variable voltage pin electronics Trip Temperature This control programs a trip point that will disconnect...

Page 248: ...Publication No 980938 Rev K Model T940 User Manual Astronics Test Systems Soft Front Panel Operation 5 167 Figure 5 99 DR3e Monitor Temperature Panel ...

Page 249: ...Model T940 User Manual Publication No 980938 Rev K Soft Front Panel Operation 5 168 Astronics Test Systems Figure 5 100 DR9 Monitor Temperature Panel Figure 5 101 UR14 Monitor Temperature Panel ...

Page 250: ...t964_setTemperatureAlarm Voltage Monitor Panel This panel is available with the following Driver Receiver boards DR3e DR9 UR14 DR4 DR3E DR9 and UR14 Voltage Monitor Panel and Controls Figure 5 102 DR3E DR9 and UR14 Voltage Monitoring Panel V Voltage This control displays the fused V bias voltage The relevant VXIplug play API functions are tat964_queryAdc tat964_queryAdcAverage ...

Page 251: ...This control is used to connect or open the EXTFORCE signal to the specified channel The relevant VXIplug play API function is tat964_setForceConnect EXTSENSE This control is used to connect or open the EXTSENSE signal to the specified channel The relevant VXIplug play API function is tat964_setSenseConnect Channel This control is used to specify the channel for the EXTFORCE EXTSENSE and Monitor S...

Page 252: ...ltage Monitoring Panel Mux Signal This control is used to program the mux tree to select the signal routed to the ADC The signal selection includes any of the channels as well as test debug signals for factory use The relevant VXIplug play API functions are tat964_setAdcMuxSignal Channel This control selects the channel number when the Mux Signal is set to DSA Channels or DSB Channels The relevant...

Page 253: ...or signal when the Mux Signal is set to Monitor A or Monitor B The relevant VXIplug play API functions are tat964_setGroupMonitorSignal AD Signal This control sets the analog diagnostic signal when the Mux Signal is set to Monitor A or Monitor B and the Positive Signal is set to AD The relevant VXIplug play API functions are tat964_setGroupMonitorSignal CD Signal or E_S Signal This control selects...

Page 254: ...e following Driver Receiver boards DR3e DR9 UR14 The temperatures on this panel will usually be less than what s shown on the Monitor Temperature panel The Monitor Temperature panel monitors the temperature near the output drivers which are usually hotter than the rest of the device However this panel shows all of the Pin Electronics device temperatures at once in their relative positions on the D...

Page 255: ...t Panel Operation 5 174 Astronics Test Systems Figure 5 105 DR9 Chip Temperature Figure 5 106 UR14 Chip Temperature The relevant VXIplug play API function is tat964_queryChannelTemp Utility Reference Monitor This panel is available when a UR14 board is installed ...

Page 256: ...ntrol are Table 5 109 UR14 Monitor Signal Settings Setting Description Front Panel ADC_IN Selects the front panel ADC_IN signal VRef5 Selects the 5V reference signal Group 1 Compare Selects the CH1 CH8 comparator level Group 2 Compare Selects the CH9 CH16 comparator level Group 3 Compare Selects the CH17 CH24 comparator level Group 4 Compare Selects the CH25 CH32 comparator level The relevant VXIp...

Page 257: ...176 Astronics Test Systems SFP Close Message This panel is used to close the soft front panel Figure 5 108 SFP Close Message If Yes is selected the following panel will be displayed Figure 5 109 SFP Reset Message The relevant VXIplug play API functions are tat964_close tat964_reset ...

Page 258: ...4 Drive High and Drive Low DR3E DR9 UR14 DR4 Compare High and Compare Low DR3E DR9 UR14 DR4 Vcommutating Vcom High and Low DR3E DR9 UR14 Current Source and Sink DR3E DR9 UR14 Current Alarm High and Low DR3E DR9 UR14 Delete Section two only DR3E DR9 UR14 DR4 CAUTION ALWAYS PERFORM DISASSEMBLY REPAIR AND CLEANING AT A STATIC SAFE WORKSTATION Performance Verification Do not attempt to calibrate the i...

Page 259: ...y Be sure to select the Voltage Range mode which is required by the application prior to calibration V and V Requirements For the DR3E DR9 and UR14 the V and V bias voltage level requirements for calibration are listed below V must be 14 V V must be 9 V The table below lists the recommended power converter settings for calibration for each voltage mode Table 6 2 Recommended Power Converter Setting...

Page 260: ...ruments unless the references and monitor paths are being re calibrated An example configuration is shown in the diagram Calibration Interval The T940 DRM should be calibrated at a regular time interval determined by the accuracy requirements of your application A one year interval is adequate for most applications Accuracy specifications are valid only when calibration is performed at regular tim...

Page 261: ... installed and interfaced to the instrument The VISA library is required Calibration is performed from the Calibration Panel in the T940 Soft Front Panel To invoke this panel access the Calibrate menu item from the Instrument menu as shown in Figure 6 1 Figure 6 1 Invoke the Calibrate DRM Panel from the SFP In addition be sure to select the Voltage Range mode which is required by the application a...

Page 262: ...ctions to follow describe the individual procedures in detail ADC Reference via EXTERNAL FORCE For DR3E DR9 and UR14 only the ADC Reference calibration is used to measure the reference voltages used to calibrate the ADC Monitor path Connect the DC calibrator to the EXTERNAL FORCE input on either DRA or DRB if installed The Export button can be used to save the calibration factors into a text file ...

Page 263: ...tems 2 Verify that the ADC Reference calibrate function is now in focus Select Measurement Delay Equipment Basic Setup Procedure 1 Select DRA or DRB if installed using the Driver Receiver switch 2 The default measurement delay is 200 ms Increase this value to give the calibration points more time to settle ...

Page 264: ... installed via the EXTERNAL FORCE input Figure 6 2 T940 DR3e DR3e Connection Diagram Figure 6 3 T940 DR9 DR9 or T940 UR14 Connection Diagram Procedure 1 Select the ADC reference to be calibrated 2 Connect the DC Calibrator using the calibration adapter cable 3 Press the Run button EXT_FORCE A Calibration Adapter Installed in J200 Calibration Adapter Installed in J9A J9B EXT_FORCE B ...

Page 265: ...ing the Update button If this step is omitted the calibration factors will revert at the next power cycle Monitor ADC The Monitor ADC calibration calculates the offset and gain of the monitor to ADC path for each channel The Verify button is available for use both before and after calibration It is recommended that the calibration be verified before the Update button is used to store the current M...

Page 266: ...ver Receiver switch 2 Use the Start and End Channel fields to select the I O and Auxiliary channels to be calibrated 3 The minimum measurement delay for this calibration is 200 ms Increase this value to give the calibration points more time to settle DRM Calibration Warmup Equipment Basic Setup Procedure 1 Allow the T940 DRM to warm to its nominal application temperature 2 Hit the Continue button ...

Page 267: ... results using the Verify button Ensure that all channels pass verification 4 Optional Check the individual gain and offset values in the field controls Verify that all offsets are near zero and that all gains are near unity 1 5 Optional Save the calibration to a file for later restore e g File Load DRA Calibration 6 Optional Update the module to the new calibration factors just obtained using the...

Page 268: ...H levels The Export button can be used to save the calibration factors into a text file for examination and later restore e g File Load DRA Calibration Select Calibrate Function Equipment Basic Setup Procedure 1 Place a check mark next the Source Sink Load menu item on the Calibrate Function menu 2 Verify that the Source Sink Load calibrate function is now in focus Run Calibration Equipment Digita...

Page 269: ... DR3e Connection Diagram Figure 6 5 T940 DR9 DR9 or T940 UR14 Connection Diagram Procedure 1 Press the Run button 2 Allow the T940 DRM to warm to its nominal application temperature 3 Enter the resistance readings taken by the DMM EXT_FORCE A Calibration Adapter Installed in J200 Calibration Adapter Installed in J9A J9B EXT_FORCE B ...

Page 270: ... levels For the DR3E DR9 and UR14 a separate offset and gain is calculated for each slew rate For the DR4 a separate offset and gain is calculated for each group offset The Verify button is available for use both before and after calibration It is recommended that the calibration be verified before the Update button is used to store the current drive high and drive low calibration factors The Expo...

Page 271: ...e calibration points more time to settle DRM Calibration Warmup Equipment Basic Setup Procedure 1 Allow the T940 DRM to warm to its nominal application temperature 2 Hit the Continue button when the required temperature is reached If the temperature reaches 80 C the process continues automatically Run Calibration Equipment Basic Setup Procedure 1 Press the Run button Use the Stop button at any tim...

Page 272: ...the offset and gain of the input comparator levels For the DR4 a separate offset and gain is calculated for each group offset The Verify button is available for use both before and after calibration It is recommended that the calibration be verified before the Update button is used to store the current drive high and drive low calibration factors The Export button can be used to save the calibrati...

Page 273: ...g the Driver Receiver switch 2 Use the Start and End Channel fields to select the I O and Auxiliary channels to be calibrated 3 The default measurement delay is 100 ms Increase this value to give the calibration points more time to settle DRM Calibration Warmup Equipment Basic Setup Procedure 1 Allow the T940 DRM to warm to its nominal application temperature 2 Hit the Continue button when the req...

Page 274: ...rify the results using the Verify button Insure that all channels pass verification 4 Optional Check the individual gain and offset values for CVH and CVL in the field controls These values are not in engineering units 5 Optional Save the calibration to a file for later restore e g File Load DRA Calibration 6 Optional Update the module to the new calibration factors just obtained using the Update ...

Page 275: ...port button can be used to save the calibration factors into a text file for examination and later restore e g File Load DRA Calibration Select Calibrate Function Equipment Basic Setup Procedure 1 Place a check mark next the CVH CVL menu item on the Calibrate Function menu 2 Verify that the Vcom High Low calibrate function is now in focus Select Start and End Channels and Measurement Delay Equipme...

Page 276: ...ration Equipment Basic Setup Procedure 1 Press the Run button Use the Stop button at any time to abort execution 2 Review the results in the Status window 3 Optional Verify the results using the Verify button Insure that all channels pass verification 4 Optional Check the individual gain and offset values for CMH and CML in the field controls These values are not in engineering units 5 Optional Sa...

Page 277: ... for use both before and after calibration It is recommended that the calibration be verified before the Update button is used to store the current drive high and drive low calibration factors The Export button can be used to save the calibration factors into a text file for examination and later restore e g File Load DRA Calibration Select Calibrate Function Equipment Basic Setup Procedure 1 Plac...

Page 278: ...sing the Driver Receiver switch 2 Use the Start and End Channel fields to select the I O and Auxiliary channels to be calibrated 3 The default measurement delay is 200 ms Increase this value to give the calibration points more time to settle DRM Calibration Warmup Equipment Basic Setup Procedure 1 Allow the T940 DRM to warm to its nominal application temperature 2 Hit the Continue button when the ...

Page 279: ...rify the results using the Verify button Insure that all channels pass verification 4 Optional Check the individual gain and offset values for Src and Snk in the field controls These values are not in engineering units 5 Optional Save the calibration to a file for later restore e g File Load DRA Calibration 6 Optional Update the module to the new calibration factors just obtained using the Update ...

Page 280: ...e used to save the calibration factors into a text file for examination and later restore e g File Load DRA Calibration Select Calibrate Function Equipment Basic Setup Procedure 1 Place a check mark next the IAL IAH menu item on the Calibrate Function menu 2 Verify that the ISource ISink calibrate function is now in focus Select Start and End Channels and Measurement Delay Equipment Basic Setup Pr...

Page 281: ...1 Press the Run button Use the Stop button at any time to abort execution 2 Review the results in the Status window 3 Optional Verify the results using the Verify button Insure that all channels pass verification 4 Optional Check the individual gain and offset values for Src and Snk in the field controls These values are not in engineering units 5 Optional Save the calibration to a file for later ...

Page 282: ...r Manual Astronics Test Systems Programmable Channel Calibration 6 25 Delete Allows the user to delete Section Two calibration data stored internally Saved calibration data can be restored using the restore feature e g File Load DRA Calibration ...

Page 283: ...Model T940 User Manual Publication No 980938 Rev K Programmable Channel Calibration 6 26 Astronics Test Systems This page was left intentionally blank ...

Page 284: ...Options 3 256 Timing Sets with 4 phases and 4 windows and 4K sequence steps 1K Timing Sets with 4 phases and 4 windows and 1K sequence steps one for each sequence step 4K Timing Sets with 1 phase and 1 window and 4K sequence steps one for each sequence step T0Cycle Period Range per Sequence step 20 ns to 65 5 μs using the 500 MHz master clock T0Cycle Timing Resolution 1 ns using the 500 MHz master...

Page 285: ... external signal levels or edges Can halt on error at slower data rates Can halt on a sync pulse used as a breakpoint Also used for single stepping The latter three require a CPU Resume see spec for additional clarification Halting on error is discussed in more detail in the Pause and Halt section of Chapter 8 for additional details about the use of halt Pause Pattern and Halt System Clutch Source...

Page 286: ... time capabilities of the Channel being used to output it Stimulus Capture Characteristics Testing Modes Dynamic Static Dynamic Mode Output Timing Sources per channel Static selection of phase 1 4 Input Timing Sources per channel Static selection of window 1 4 Data Output Formats per channel Force lo hi tri state Format NR RT R0 R1 RC Complement Surround Output the Phase or its complement used to ...

Page 287: ...Step Stimulus and Response capture timing defined by Pulse Generator assert and de assert timing set the Pulse Generator for Single Start Resolution and range based on the Pulse Generation settings Standby Sequence Step must have a period greater than the de assert timing Static Mode Type 2b available on F W 0 21and later Utilizes an independent static stimulus response path that doesn t alter the...

Page 288: ... allow windows to effectively close at the end of the T0Cycle Resolution 1 master clock Range 2 63 master clocks Sequencer Characteristics General Sequencers 2 per Digital Resource Module Channels 32 per sequencer Modes Static Dynamic Sequence Memory Sequence Size 1024 or 4096 Steps Sequence Loop Counters Loop Counters 16 Loop Count can be different each time or continuous Loop counters may be nes...

Page 289: ...e or Low state Sync Pulse Outputs Outputs per Sequencer 2 Modes Start of Sequence Start of Sequence Step Offset Range 0 1M patterns Pulse Width 1 4095 patterns AUX Outputs Sync Pulses 2 Sequence Flags 2 Sequence Idle Active T0Cycle Waveforms Phases Windows A multitude of other signals Sequence Standby Characteristics A one word continuous sequence step that may be used to output standby data on po...

Page 290: ...maximum execution time of a dynamic pattern set independently of pauses halts and external clocks On timeout sets all outputs to tri state Can be disabled Range 40 ns to 86 seconds Resolution 20 ns Handshaking See Pause function Master Clock MCLK Internal Oscillator 500 MHz Accuracy 50 ppm Internal Synthesizer 40 KHz to 500 MHz Internal Reference 20 MHz or VXICLK10 Internal Synthesizer Resolution ...

Page 291: ...10 s in decade steps Aperture Window Accuracy 0 1 50 ppm Frequency Period Measurement Resolution 4 Digits with a 1 ms Aperture 5 Digits with a 100 ms Aperture 6 Digits with a 10 s Aperture Time Interval Functions Between Inputs 1 2 Positive Negative Pulse Width of Input 1 Time Interval Range 2 ns to 4 29 s Time Interval Resolution 1 ns Time Interval accuracy 1 count input comparator threshold unce...

Page 292: ...ck VXI Triggers TTL and ECL Linked Trigger Bus Any Aux channel Counter Input Pulse Resolution 10 ns 20 ns Run Mode Continuous Continuous Start Single Start Single Step Period 10 ns Resolution Min 20 ns Max 42 94967297 s 20 ns Resolution Min 40 ns Max 85 899345960 s Delay 10 ns Resolution Min 20ns Max 42 94967297 s 20 ns Resolution Min 20ns Max 85 899345960 s Width 10 ns Resolution Min 0ns Max 42 9...

Page 293: ...l I O The DB is isolated from the front panel via the Driver Receiver board s Refer to the appropriate appendix for the front panel specifications for the installed Driver Receiver board VXI Interface Interfaces Supported Register based operation Data Transfers Address A16 and A24 A32 Data D16 D32 VXI Feature Usage TTLTRG0 7 ECLTRG0 1 Triggering driver disable channel tests DRS sync check and erro...

Page 294: ...0 04 0 37 Idyn A 0 0 0 03 0 01 0 02 VXI Current Requirements With 2 DR3s installed V 24 12 5 2 5 2 Ipeak A 0 02 0 03 9 5 0 26 5 4 Idyn A 0 01 0 01 0 53 0 01 0 04 Front Panel PWR Current Requirements channels unloaded per DR3 V 3 8 A max 2 9 A typ 21 5 V V 4 3 A max 3 4 A typ 10 5 V MTBF ground benign T940 180 885 hours Dimensions Single slot C size VXI module 30 x 260 x 350 mm EMC Council Directiv...

Page 295: ...Model T940 User Manual Publication No 980938 Rev K Specifications 7 12 Astronics Test Systems This page was left intentionally blank ...

Page 296: ... capability when it comes to Jumping or Halting on various Pass Fail conditions in both Pipelined and non Pipelined modes The counting or logging of Errors in the Error Address Memory EAM Single Stepping and Record Modes will also be covered since they are interrelated This section discusses these topics using the Soft Front Panel SFP but VXIplug play API calls and Application Resource Interface A...

Page 297: ...ny of the other Sequencers may be excluded Those excluded may be simply unused be independent or for a given DRM could be Linked In the latter two cases they are separate instruments from the remaining sequencers which make up the DRS Coupled A term that s only used when another sequencer is coupled to the Master in a DRS Before getting into the details of Jumping Halting Counting and Logging ther...

Page 298: ...ese six are all of the signals that are potentially useful Those that are not needed may be excluded For example Static Pulse may be excluded if channels will not be used in Static Mode anywhere in the DRS The panel automatically handles the direction and sense of these signals thus the Direction and Invert fields are dimmed Note Sequence Reset and Master Reset are automatically handled in the S W...

Page 299: ...e operated From the same Configure Module panel select VXI Triggers for the Data Sequencer A and or B depending on whether that Sequencer is included in the DRS configuration or not The relevant VXIplug play API and ARI functions are API tat964_setTtlTriggers tat964_setEclTriggers ARI AssignPatTimeGroup AssignPtgTrigger Additional signals required to be coupled along the backplane to form the DRS ...

Page 300: ...id Needed whenever Pass Valid Mode is enabled Error must also be connected coupled when Pass Valid is used Halted Allows connected coupled Sequencers to have their Pattern Data and Record memories accessible when halted DRS Sync Allows one to detect and create an event that says that that a connected coupled Sequencer is out of sync with the Master Sequencer Sequence Reset Allows a Sequence Reset ...

Page 301: ...c Mode is being used The signals above which are desired for a DRS configuration must be setup on the same TRG buses on the Master and each coupled Sequencer Warning Do not program the same TRG Bus for Sequencers which are not a part of the DRS Step Record Mode Step Record Mode is programmed in each Sequencer Step On the SFP it is set on the Edit Data Sequencer A B Sequence Steps panel The relevan...

Page 302: ... Errors Record Response Record Response The first choice means that nothing will be recorded in the Record Memory for any pattern in this step But this means different things based on the Record Type See the Record Type section below for more information The second entry provides two choices This is programmed on the Config Configure Module panel as shown in Figure 8 4 below The relevant VXIplug p...

Page 303: ...g play API and ARI functions are API tat964_setRecordParameter ARI AssignPtgRecordType Figure 8 6 Setting the Record Type Using the Configure DSA Settings Panel The two choices are Normal Indexed Setting the Record Type to Normal records into the Record Memory at the same address which corresponds to the Data Pattern Thus when looping a Step or repeating a Step at some later point during the Prima...

Page 304: ...y unnecessarily with zeros Counting and Logging Errors Errors can be counted for Independent Sequencers Linked Sequencers or multiple Sequencers which are part of a DRS Similarly Errors can be logged into the EAM for Independent Sequencers Linked Sequencers or multiple Sequencers which are part of a DRS For both of these circumstances the Errors can be non qualified Errors or Qualified Errors When...

Page 305: ... TEST row for each pattern column a b sets BERREN true whereas an n sets it false Thus in the example above patterns 1 3 5 6 have BERREN set whereas patterns 2 4 do not have BERREN set The Basis for Counting Errors is set on the CONFIG Data Sequencer A B Settings Panel The relevant VXIplug play API and ARI functions are API tat964_setErrorParameters ARI AssignPatTimeGroup ...

Page 306: ... the Configure DSA Settings Panel The Basis for Logging Errors into the EAM is set on the same Panel The relevant VXIplug play API and ARI functions are API tat964_setErrorParameters ARI AssignPatTimeGroup Figure 8 9 Setting Error Address Basis in the Configure DSA Settings Panel In both cases the available choices are the same Local ...

Page 307: ...ount DRS Linked Errors Qual DRS Linked Don t Count Errors Count BERREN Qual DRS Linked Errors Count BERREN Qual DRS Linked Errors Count BERREN Qual DRS Linked Errors For logging Errors into the EAM refer to Table 8 5 Table 8 5 Cross Reference of Step Record Mode to Error Address Basis Step Record Mode Error Address Basis None Record Count Record Error Record Response Local Don t log any Errors Don...

Page 308: ...lled a non zero pipeline depth or pipelined A zero pipeline depth is primarily used when it s desired to perform a Jump on Pass Fail in a Seq Step where the deciding Error may occur on even the last Pattern of the Seq Step This allows one to Halt immediately on Patterns that have a Fail or Pass There are performance limitations for the zero pipeline depth covered in the Performance Considerations ...

Page 309: ...nel The setting for a pipeline depth of 8 is shown Jumping and Halting on Pass Fail Similar to the Counting and Logging of Errors there is a Basis for Jumping and Halting on Pass Fail conditions Jumping and Halting is programmed on the same panel as before The relevant VXIplug play API and ARI functions are API tat964_setPassFailParameter ARI AssignPatTimeGroup ...

Page 310: ...qualified Pass Fail Basis in this case is based on CONDEN Condition Enable CONDEN is programmed in the Pattern Data as follows PnP tat964_setPatternTestEnable The relevant VXIplug play API and ARI functions are API tat964_setPatternTestEnable ARI LoadPtgStepExpectedPatternBin LoadPtgStepPatternChar Figure 8 12 Setting the Pass Fail Basis in the Configure DSA Settings Panel ...

Page 311: ... into the Pipeline Qual Local Insert CONDEN Qual Local Errors and PV into the Pipeline Insert CONDEN Qual Local Errors and PV into the Pipeline Insert CONDEN Qual Local Errors and PV into the Pipeline Insert CONDEN Qual Local Errors and PV into the Pipeline DRS Linked Insert DRS Linked Errors and PV into the Pipeline Insert DRS Linked Errors and PV into the Pipeline Insert DRS Linked Errors and PV...

Page 312: ...e 8 13 Setting the Jump Condition in the Edit DSA Sequence Step Panel On this pull down you ll see that six Jump Conditions based on Pass and Fail The Halt Modes are Programmed on the Execute DSA DSB panel The relevant VXIplug play API and ARI functions are API tat964_setHaltMode ARI AssignPtgHaltMode ...

Page 313: ...sed for Jumping and or Halting on Pass Fail conditions Halting on a Pass Fail condition may be done on a Pattern a Sequence Step or a Sequence as though the Burst Count is set to 1 Jumping on a Pass Fail condition may be done on a Sequence Step or Sequence as though the Burst Count is set to 1 With default settings Pass Fail for a Sequence Step represents the cumulative results for that Sequence S...

Page 314: ...Sequence This mode on operation is enabled by Pass Valid Enable a static setting This is set on the Config Data Sequencer A B Settings panel The relevant VXIplug play API and ARI functions are API tat964_setPassFailParameters ARI AssignPtgPipelineParameters Figure 8 15 Setting the Halt Mode in the Execute DSA Panel If there is neither a Valid Pass nor a Fail it is called Indeterminate NOT Pass is ...

Page 315: ... Pass Valid Mode is enabled none of the qualified patterns in the Seq Step can have a Capture Fault for Pass to occur Pipelined handling of Pass Fail with default settings Since the Error signal and Pass Valid if used are delayed by the pipeline these signals will not be aligned with the Jump Test made at the end of an individual Sequence Step or at the end of a Primary Sequence Thus to make a cor...

Page 316: ...il Clear Control in the Edit DSA Sequence Step Panel Default is one of the default settings included above Mask means that at the end of this Sequence Step that the Pass Fail accumulator will not be cleared Pass Fail Option 2 This option disables the Step Pass Fail accumulator but not for the Sequence Pass Fail accumulator Thus the Pass Fail status on any particular pattern occurs exactly N patter...

Page 317: ...re two options for clearing a pipeline of depth N to NOT Fail not generate an Error a If the Jump Basis is not qualified use a Seq Step with a jump to self for a count of N For the one Pattern in this step have an expect condition which is known to NOT Fail not generate an Error b If the Jump Basis is qualified use a Seq Step with a jump to self for a count of N and set CONDEN low e g b or n for t...

Page 318: ...Pass Valid if used are not delayed by the pipeline these signals will be aligned with the Jump Test made at the end of an individual Sequence Step or at the end of a Sequence Thus all the patterns in the Sequence Step or Sequence will be accumulated and none outside of the Sequence Step will be included But there is one option as follows Pass Fail Option 1 This option allows one to accumulate Pass...

Page 319: ...apture Mode of none or an Expect and a Capture Mode but without appropriate Window edges within the Pattern period Capture Faults automatically generate an Error for that Pattern The channel s with a Capture Fault can be queried which may help narrow down where the Capture Fault occurred Note Whereas a Valid Pass only requires one channel with an Expect and Capture Mode a Capture Fault is generate...

Page 320: ...typically used for single stepping Pattern Step Sequence Sync 1 Sync 2 These latter two are actually Sync Pulses set on the Execute Panel by clicking Set Sync The relevant VXIplug play API and ARI functions are API tat964_setSyncEvent tat964_setSyncParameters ARI AssignPtgSyncPulse Each Sync Pulse can be set to start from the beginning of the Sequence or a specified Seq Step and then have an Offse...

Page 321: ...RI ResumePtg The last six types of Halt Modes cover Halt Modes on various types of Pass Fail conditions In these modes set the desired condition and then click Execute The relevant VXIplug play API and ARI functions are API tat964_executeSequence ARI ExecutePtg Do not click Halt before Execute Click Resume when you want to proceed to the next conditional Halt if more are expected As before the Hal...

Page 322: ...al operation to continue but there are exceptions Applications A Halt can be used to o Replicate the function of a System Clutch o Halt on Error o Halt on a pattern using a Sync pulse or external signal o Establish a breakpoint o Do single stepping o Do Probe stepping A Pause can be used to o Replicate the function of a Pattern Clutch o Pause the data output when doing a handshake o Pause on a pat...

Page 323: ...lure Timing requirements for a Halt on Pattern Error Step Failure or Burst Failure o See the Jumping Halting Counting and Logging on Pass Fail section for the detailed timing requirements and additional information The CPU can also perform a Resume at any time which can allow normal operation to proceed This CPU resume can be used to o Resume after single stepping o Resume other types of Halt cond...

Page 324: ... o The Halt Edge test flip flop is cleared just before the beginning of the Sequence or with a CPU Resume or Single Step option 3 Halt Examples Halt on a Pattern Error o Set the Single Step Type to Halt on Pattern Error Halt on Pattern 6 in Sequence Step 4 like a breakpoint o Set the Single Step Type to Halt on Sync1 o Setup Sync Pulse 1 to begin a Sync Pulse on Pattern 6 in Sequence Step 4 with a...

Page 325: ...g will be corrupted See the Jumping Halting Counting and Logging on Pass Fail section for the detailed timing requirements and additional information Pause Operations A Pause operation is defined within a Sequence Step Thus it can be constrained to occur only at particular times during the Sequence Pause Test Condition Choices settable in each Seq Step o None o Always o Pause Test 1 True or Not Tr...

Page 326: ... Edge o Falling Edge Pause Resume Options settable in each Seq Step o None o Pattern Delay Timer 1 used to Resume after a fixed delay o Pattern Delay Timer 2 used to Resume after a fixed delay o Pattern Timeout Timer Pattern Delay Timeout Timer static settings o Range 20 ns to 43s o Resolution 10ns Pause Timing Considerations o An external signal used to initiate the pause must occur in a timely m...

Page 327: ... options o CPU Resume o Mated External Resume there s one for each Pause Test source o Pattern Delay Timer timeout Phase Test 1 4 Resume options o CPU Resume o Mated External Resume there s one for each Phase Test source o Pattern Delay Timer timeout Pause Examples A Handshake example Pause on Phase 4 FE right after the output data is formatted and before the input data is to be captured of Sequen...

Page 328: ...ill not occur When Paused the CPU cannot access the Pattern Record or Probe memories For 0 23 F W a Pause based on a level can only be cleared by removing the level causing the Pause Changing the Pause Test Condition will not clear a Pause nor will a CPU Resume a Pattern Delay Timeout or a Sequence Reset For 0 23 F W the Phase Pause edge may occur as early as 0ns T0 but not later than 16ns before ...

Page 329: ...p that may be run before and or after the Primary Sequence The Idle Sequence run after a Primary Sequence may be different than the one run before a Primary Sequence An Idle Sequence always runs continuously and may output one or more Patterns but response data is ignored A Finishing Sequence is the Seq Step that is run after the Primary Sequence It may be an Idle Sequence or a Standby Sequence A ...

Page 330: ... and other purposes 4 bits Pause Resume Options used for Pattern Delay and Pattern Timeout 2bits Record Capture Type 2 bits The first 5 items above are used to control the execution of the Sequence Steps Here are some examples Unconditional Jumps o Select a Jump Always Test Condition o Designate the Jump Sequence Address Conditional Jumps o Select a Test Condition o Designate the Jump Sequence Add...

Page 331: ...ter is used Bit two the Use Counter Once UCO bit is programmed by the user If UCO is set the CA bit will not be reset when exiting the loop thus the counter cannot be re used once the count is exhausted If not set the CA bit is reset when the count is exhausted and the next sequence step begins Loops can be done around one or more Sequence Steps and the group of sequence steps need not be consecut...

Page 332: ...ctive LC Loop Count from the Sequence Step LCD Loop Count Done BCD Burst Count Done BC Burst Continuous UCO Use Counter Once LAST A flag used to denote that a LSTSEQ had a jump to a SUBRT thus the Return needs to be altered The general order of precedence is Jump Return Last Sequence Next Sequence Jump LSTSEQ RTN SUBRT CLOOP Action Comments 1 0 0 0 0 0 Proceed to the next Seq Step 2 1 0 0 0 0 Jump...

Page 333: ...designated Loop Counter set CA 1 set the IN_SUB flag save the Return Seq addr and jump to JSA If CA 1 and NOT LCD decrement the loop counter and jump to JSA If CA 1 and LCD reset CA if UCO 0 and proceed to the next Seq Step Otherwise proceed to the next Seq Step 9 0 0 1 0 0 If IN_SUB jump to the Return Seq and clear the IN_SUB flag Otherwise proceed to the next Seq Step also set a fault flag 10 1 ...

Page 334: ... Seq addr and jump to JSA If IN_SUB jump to the Return Seq and clear the IN_SUB flag also set a fault flags 15 0 0 1 1 1 If IN_SUB jump to the Return Seq and clear the IN_SUB flag Otherwise proceed to the next Seq Step also set a fault flags 16 1 0 1 1 1 If LC 0 and IN_SUB jump to the Return Seq and clear the IN_SUB flag If LC 0 and CA 0 and NOT IN_SUB load the designated Loop Counter set CA 1 set...

Page 335: ...q loops or finishes Otherwise the Seq loops or finishes 21 0 1 0 1 0 The Seq loops or finishes 22 1 1 0 1 0 If NOT IN_SUB set the IN_SUB flag set the LAST flag and jump to JSA Otherwise the Seq loops or finishes also set a fault flag 23 0 1 0 1 1 The Seq loops or finishes 24 1 1 0 1 1 If LC 0 the Seq loops or finishes If LC 0 and CA 0 and NOT IN_SUB load the designated Loop Counter set CA 1 set th...

Page 336: ...o JSA If CA 1 and NOT LCD decrement the loop counter and jump to JSA If CA 1 and LCD reset CA if UCO 0 also if IN_SUB jump to the Return Seq and clear the IN_SUB flag Otherwise the Seq loops or finishes also set a fault flag 29 0 1 1 1 0 If IN_SUB jump to the Return Seq and clear the IN_SUB flag Otherwise the Seq loops or finishes also set a fault flag 30 1 1 1 1 0 If NOT IN_SUB set the IN_SUB fla...

Page 337: ...VXI Backplane Trigger Bus Trigger Bus description TTLTRG Bus 8 VXI backplane signals normally active low ECLTRG Bus 2 VXI backplane signals normally active high Trigger Bus Applications Inter module communications for Sequencers configured in a Master Slave configuration o Communicating a Trigger for a Conditional Jump Error with or w o Pass Valid Channel Test o Communicating a Synchronization Sig...

Page 338: ... to another instrument The signals driving out onto these buses or coming in from these buses can be inverted Normal Operation Example To do a Jump Test on an Aux Input located on a Slave Sequencer o Select the TRG Bus to be used and select the Aux signal to drive it o Invert the output if the Aux signal is active low o On the Master select the same TRG Bus signal and use a High or Rising Edge tes...

Page 339: ... test condition Notes 1 Local versions of the TRG signals are used when DSA and DSB on the same module are linked Thus Channel Tests will function as above without using the backplane TRG Bus lines 2 The TTLTRG Bus has a weak pullup thus the risetime will be quite slow As such the trailing edge of an active low signal will be delayed up to 40ns more than the leading edge Triggering on a falling ed...

Page 340: ...cation Development Environment ARGCS Agile Rapid Global Combat Support Assert Rising edge of a Phase ARI Application Resource Interface ATLAS Abbreviated Test Language for All Systems AUX Auxiliary Bipolar Sources and sinks current single ended CAD Computer Aided Design CPP Clocks per Pattern CH Channel signal Channel Test Allows any channel of the installed Driver Receiver boards to be used as a ...

Page 341: ...equencer A DSB Digital Sequencer B DUT Device Under Test DVH Drive Voltage High DVL Drive Voltage Low ECL Emitter Coupled Logic ECL TRG VXI ECL trigger EN Enable Error A channel error is determined by comparing the channel response to the expect mask conditions of the Pattern data GND_REF Ground reference output from the pin electronics devices Good 0 A signal generated when an input signal is les...

Page 342: ...rrors section of Chapter 8 See also Valid Pass below Pattern One stimulus applied to and or one response received from the UUT Sometimes called a Word or Vector Pattern Set A Pattern Set is one or more consecutive channel patterns PBUT Probe button input signal to the Sequencer for support of remote probe operations PMODE Control signal from the Sequencer for support of remote probe operations Pri...

Page 343: ...O_CLK System Clock TPS Test Program Set TTL TRG VXI TTL Trigger UR14 Utility Resource Board Probe and 32 channel open collector I O UUT Unit Under Test V Positive supply voltage provided by the Power Converter which is used to power the Pin Electronics devices In addition external power may be applied to V via an optional front panel power connector V Negative supply voltage provided by the Power ...

Page 344: ...0 User Manual Astronics Test Systems Terms and Acronyms A 5 VOL Voltage Output Low Level max VXI VME Extensions for Instrumentation VXI_INT VXI Interrupt Signals The backplane interrupt signals WCEM Microsoft Windows CIIL Emulation Module ...

Page 345: ...Model T940 User Manual Publication No 980938 Rev K Terms and Acronyms A 6 Astronics Test Systems This page was left intentionally blank ...

Page 346: ...table output impedance Auxiliary channels Four LVTTL with selectable output impedance and resistive input load Four LVTTL Four ECL single ended or differential Front Panel Connectors The front panel of the DR1 Driver Receiver is shown in Chapter 3 Block Diagram This section describes the basic hardware configuration of the DR1 Driver Receiver DRA or DRB The DR1 is comprised of four major logic sec...

Page 347: ...5 8 AUX RH 5 8 AUX DATA 9 12 AUX EN 9 12 AUX RH 9 12 AUX 5 8 AUX 9 12 AUX 9 12 AUX DATA 1 4 AUX EN 1 4 AUX RH 1 4 AUX RL1 CH DATA 1 32 CH EN 1 32 CH RH 1 32 CH RL 1 32 MP SIG CBUS I O CONTROL AUX 1 4 CH 1 32 I O CONTROL I O CONTROL I O CONTROL MF SIG Figure B 1 DR1 Driver Receiver Block Diagram Auxiliary Driver Receiver I O Figure B 2 illustrates the configuration and control of AUX5 8 LVTTL and A...

Page 348: ...Response High inputs to the Data Sequencer from the LVTTL input buffers AUX RH 9 12 Auxiliary Response High inputs to the Data Sequencer from the ECL input buffers AUX DATA 9 12 Auxiliary active high Data outputs from the Data Sequencer to the ECL output buffers AUX EN 9 12 Auxiliary active low Data outputs from the Data Sequencer to the ECL output buffers EN 9 12 Auxiliary Enable outputs from the...

Page 349: ...and auxiliary data output signals from the Data Sequencer to the LVTTL output drivers EN Channel and auxiliary enable output signals from the Data Sequencer to the LVTTL output drivers RH Response High input signals to the Data Sequencer from the LVTTL input receivers 1 good 1 0 good 0 RL Response Low input signals to the Data Sequencer from the LVTTL input receivers 0 good 0 1 good 1 AUX 1 4 Four...

Page 350: ...TROL Signals used to program firmware and NV DATA DR1 Characteristics Table B 1 DR1 Characteristics Description Characteristics Digital I O Type LVTTL 74LVC2G125 Channels 32 single ended SE per I O board Per channel relay isolation Output Voltage VOL 0 55 V max VOH 2 4 V min Output Drive Current typical Source Sink 24 mA Output Impedance Program selectable per pin Direct or 100 Ω Series 001 Direct...

Page 351: ...t controlled 10 C to 30 C 5 to 95 5 RH 30 C to 40 C 5 to 75 5 RH 40 C to 50 C 5 to 55 5 RH Altitude 10 000 ft Cooling Required 10 C Rise 2 DR1s Max 4 68 lps 8 9 mmH2 0 Typ 4 60 lps 4 5 mmH2 0 Front Panel Current Requirements NA MTBF ground benign DR1 257 335 hours T940 180 885 hours T940 DR1 106 220 hours T940 DR1 DR1 66 922 hours Dimensions 20 x 114 x 305 mm EMC Council Directive 89 336 EEC Emiss...

Page 352: ...5 A 42 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX6 A 44 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX7 A 84 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX8 A 86 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX9 A 88 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2V AUX9 A 89 Bi directional General Purpose ECL I O pi...

Page 353: ...ND 2 CH1 52 CH17 3 SIG_GND 53 SIG_GND 4 CH2 54 CH18 5 SIG_GND 55 SIG_GND 6 CH3 56 CH19 7 SIG_GND 57 SIG_GND 8 CH4 58 CH20 9 SIG_GND 59 SIG_GND 10 CH5 60 CH21 11 SIG_GND 61 SIG_GND 12 CH6 62 CH22 13 SIG_GND 63 SIG_GND 14 CH7 64 CH23 15 SIG_GND 65 SIG_GND 16 CH8 66 CH24 17 SIG_GND 67 SIG_GND 18 CH9 68 CH25 19 SIG_GND 69 SIG_GND 20 CH10 70 CH26 21 SIG_GND 71 SIG_GND 22 CH11 72 CH27 23 SIG_GND 73 SIG_...

Page 354: ...ce AUX1 B 34 Bi directional General Purpose LVTTL I O pin AUX2 B 36 Bi directional General Purpose LVTTL I O pin AUX3 B 38 Bi directional General Purpose LVTTL I O pin AUX4 B 40 Bi directional General Purpose LVTTL I O pin AUX5 B 42 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX6 B 44 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX7 B 84 Bi directional General Pu...

Page 355: ...Table B 6 DR1 Pinout by Pin Number DRB Pin No Signal Pin No Signal 1 SIG_GND 51 SIG_GND 2 CH33 52 CH49 3 SIG_GND 53 SIG_GND 4 CH34 54 CH50 5 SIG_GND 55 SIG_GND 6 CH35 56 CH51 7 SIG_GND 57 SIG_GND 8 CH36 58 CH52 9 SIG_GND 59 SIG_GND 10 CH37 60 CH53 11 SIG_GND 61 SIG_GND 12 CH38 62 CH54 13 SIG_GND 63 SIG_GND 14 CH39 64 CH55 15 SIG_GND 65 SIG_GND 16 CH40 66 CH56 17 SIG_GND 67 SIG_GND 18 CH41 68 CH57 ...

Page 356: ...GND 48 SIG_GND 98 NC 49 NC 99 SIG_GND 50 NC 100 NC PWR Connector When connected to an installed DR1 board the PWR connector Figure B 5 only utilizes the pins for the multi function signal MFSIG and signal ground GND The power pins are not connected to the board Figure B 5 Front Panel PWR Connector When installing the Driver Receiver Board be sure that the correctly marked PWR cable inside the modu...

Page 357: ...7 PWR Connector Name Pin No Description DRB MFSIG 2 Output Multi function signal DRB DRB GND 4 Power supply signal return DRB DRA MFSIG 6 Output Multi function signal DRA DRA GND 7 Power supply signal return DRA Calibration Table B 8 Calibration Settings Inter module timing deskew Static End of cable deskew Static ...

Page 358: ... LVDS Four LVTTL Four ECL single ended or differential Front Panel Connectors The front panel of the DR2 Driver Receiver is shown in Chapter 3 Block Diagram This section describes the basic hardware configuration of the DR2 Driver Receiver DRA or DRB The DR2 is comprised of four major logic sections as shown in Figure C 1 Auxiliary Driver Receiver I O DR2 Driver Receiver I O Control Logic Firmware...

Page 359: ... AUX RH 5 8 AUX DATA 9 12 AUX EN 9 12 AUX RH 9 12 AUX 5 8 AUX 9 12 AUX 9 12 AUX DATA 1 4 AUX EN 1 4 AUX RH 1 4 AUX RL1 CH DATA 1 32 CH EN 1 32 CH RH 1 32 CH RL 1 32 MP SIG CBUS I O CONTROL AUX 1 4 CH 1 32 I O CONTROL I O CONTROL MF SIG AUX 1 4 CH 1 32 Figure C 1 DR2 Driver Receiver Block Diagram Auxilliary Driver Receiver I O Figure C 2 illustrates the configuration and control of AUX5 8 LVTTL and...

Page 360: ...Response High inputs to the Data Sequencer from the LVTTL input buffers AUX RH 9 12 Auxiliary Response High inputs to the Data Sequencer from the ECL input buffers AUX DATA 9 12 Auxiliary active high Data outputs from the Data Sequencer to the ECL output buffers AUX EN 9 12 Auxiliary active low Data outputs from the Data Sequencer to the ECL output buffers EN 9 12 Auxiliary Enable outputs from the...

Page 361: ...auxiliary enable output signals from the Data Sequencer to the LVDS output drivers RH Response High input signals to the Data Sequencer from the LVDS input receivers 1 good 1 0 good 0 RL Response Low input signals to the Data Sequencer from the LVDS input receivers 0 good 0 1 good 1 AUX 1 4 Four positive differential LVDS signals used to input or output test signals See Configuring the AUX Channel...

Page 362: ...er assembly revision is stored in an on board EEPROM Signal Descriptions I O CONTROL Signals used to program firmware and NV DATA DR2 Characteristics Table C 1 DR2 Characteristics Description Characteristics Digital I O Type LVDS SN65LVDM176D Channels 32 differential per Driver Receiver board Output Voltage VOL 454 mV max VOH 247 mV min Differential Input Voltage 200 mV min Output Drive Current ty...

Page 363: ...Not controlled 10 C to 30 C 5 to 95 5 RH 30 C to 40 C 5 to 75 5 RH 40 C to 50 C 5 to 55 5 RH Altitude 10 000 ft Cooling Required 10 C Rise 2 DR2s Max 2 4 lps 8 9 mmH2 0 Typ 2 4 lps 4 5 mmH2 0 Front Panel Current Requirements NA MTBF ground benign DR2 305 905 hours T940 180 885 hours T940 DR2 113 670 hours T940 DR2 DR2 69 804 hours Dimensions 20 x 114 x 305 mm EMC Council Directive 89 336 EEC Emiss...

Page 364: ...tional General Purpose LVDS Negative I O pin AUX2 A 36 Bi directional General Purpose LVDS Positive I O pin AUX2 A 37 Bi directional General Purpose LVDS Negative I O pin AUX3 A 38 Bi directional General Purpose LVDS Positive I O pin AUX3 A 39 Bi directional General Purpose LVDS Negative I O pin AUX4 A 40 Bi directional General Purpose LVDS Positive I O pin AUX4 A 41 Bi directional General Purpose...

Page 365: ...CL I O pin 51 1 Ohm to 2 V AUX12 A 94 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX12 A 95 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V PBUT A 46 Bi directional Probe Button Input PMODE A 47 Output Probe Support Output BCLK A 96 Output Reserved Table C 4 DR2 Pinout by Pin Number DRA Pin No Signal Pin No Signal 1 SIG_GND 51 SIG_GND 2 CH1 52 CH17 3 CH1 53 CH17 4 CH2 54...

Page 366: ... CH15 80 CH31 31 CH15 81 CH31 32 CH16 82 CH32 33 CH16 83 CH32 34 AUX1 A 84 AUX7 A 35 AUX1 A 85 SIG_GND 36 AUX2 A 86 AUX8 A 37 AUX2 A 87 SIG_GND 38 AUX3 A 88 AUX9 A 39 AUX3 A 89 AUX9 A 40 AUX4 A 90 AUX10 A 41 AUX4 A 91 AUX10 A 42 AUX5 A 92 AUX11 A 43 SIG_GND 93 AUX11 A 44 AUX6 A 94 AUX12 A 45 SIG_GND 95 AUX12 A 46 PBUT_A 96 BCLK A 47 PMODE_A 97 SIG_GND 48 SIG_GND 98 NU 49 NU 99 SIG_GND 50 NU 100 NU...

Page 367: ...X4 B 41 Bi directional General Purpose LVDS Negative I O pin AUX5 B 42 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX6 B 44 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX7 B 84 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX8 B 86 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX9 B 88 Bi directional General Purpose ECL I O pin 51...

Page 368: ...7 60 CH53 11 CH37 61 CH53 12 CH38 62 CH54 13 CH38 63 CH54 14 CH39 64 CH55 15 CH39 65 CH55 16 CH40 66 CH56 17 CH40 67 CH56 18 CH41 68 CH57 19 CH41 69 CH57 20 CH42 70 CH58 21 CH42 71 CH58 22 CH43 72 CH59 23 CH43 73 CH59 24 CH44 74 CH60 25 CH44 75 CH60 26 CH45 76 CH61 27 CH45 77 CH61 28 CH46 78 CH62 29 CH46 79 CH62 30 CH47 80 CH63 31 CH47 81 CH63 32 CH48 82 CH64 33 CH48 83 CH64 34 AUX1 B 84 AUX7 B 35...

Page 369: ... only utilizes the pins for the multi function signal MFSIG and signal ground GND The power pins are not connected to the board Figure C 5 Front Panel PWR Connector When installing the Driver Receiver Board be sure that the correctly marked PWR cable inside the module is connected to its specific board the cable marked DRA for the DRA board and marked DRB for the DRB board Incorrect installation m...

Page 370: ...7 PWR Connector Name Pin No Description DRB MFSIG 2 Output Multi function signal DRB DRB GND 4 Power supply signal return DRB DRA MFSIG 6 Output Multi function signal DRA DRA GND 7 Power supply signal return DRA Calibration Table C 8 Calibration Settings Inter module timing deskew Static End of cable deskew Static ...

Page 371: ...Model T940 User Manual Publication No 980938 Rev K DR2 Driver Receiver Board C 14 Astronics Test Systems This page was left intentionally blank ...

Page 372: ...Selectable resistive input load 8 choices to a programmed voltage Selectable slew rate 0 25 V ns to 1 3 V ns 12 50 ohm selectable output impedance Over current detection Over voltage detection protection Auxiliary channels Four variable voltage Four LVTTL Four ECL single ended or differential Front Panel Connectors The front panel of the DR3e Driver Receiver is shown in Chapter 3 Block Diagram Thi...

Page 373: ...UX DATA 1 4 AUX EN 1 4 AUX RH 1 4 AUX RL1 CH DATA 1 32 CH EN 1 32 CH RH 1 32 CH RL 1 32 MP SIG CBUS AUX 1 4 CH 1 32 MF SIG OC 1 32 GND_REF TEMPMON EXTFORCE MONITOR INTERRUPT EXTSENSE OVERVOLT V V PC V V DUT_GND EXTSENSE DUT_GND V V I O CONTROL I O CONTROL TEMPMON OVERVOLT EXTFORCE GND_REF MONITOR V V FP DUT_GND FP I O CONTROL I O CONTROL Figure D 1 DR3e Driver Receiver Block Diagram Auxiliary Driv...

Page 374: ... Response High inputs to the Data Sequencer from the LVTTL input buffers AUX RH 9 12 Auxiliary Response High inputs to the Data Sequencer from the ECL input buffers AUX DATA 9 12 Auxiliary active high Data outputs from the Data Sequencer to the ECL output buffers AUX EN 9 12 Auxiliary active low Data outputs from the Data Sequencer to the ECL output buffers EN 9 12 Auxiliary Enable outputs from th...

Page 375: ...ONTROL LOGIC MONITOR GND_REF EXTFORCE OVERVOLT TEMPMON TEMP DR3e Only Figure D 3 DR3e Driver Receiver I O Block Diagram Signal Descriptions DATA Channel and auxiliary data output signals from the Data Sequencer to the programmable output drivers EN Channel and auxiliary enable output signals from the Data Sequencer to the programmable output drivers OC Over Current detect from the programmable Dri...

Page 376: ...n the Channel I O levels This signal is used with the internal ADC but a buffered version also comes out the Front Panel GND_REF This is the ground reference output signal from the Pin Electronics devices It is used with MONITOR to make accurate ADC measurements A buffered version also comes out the Front Panel EXTFORCE External Force is an analog I O signal which is connected to all of the Pin El...

Page 377: ...R3e Control Logic Block Diagram Signal Descriptions MP SIG Multi Purpose signal from the data sequencer CBUS An internal Control Bus connecting the digital board to the Driver Receiver board INTERRUPT Real time signal generated from the power and temperature monitor data V PC Positive bias power required for operation of the Pin Electronics devices from the T940 power converter V PC Negative bias ...

Page 378: ...used with MONITOR to make accurate ADC measurements V Fused and switched positive bias power required for operation of the Pin Electronics devices V Fused and switched negative bias power required for operation of the Pin Electronics devices OVERVOLT Real time over voltage detector circuit monitors Driver and Receivers to protect the pin electronics Also clamps the inputs to the V rails DUT_GND Ei...

Page 379: ...s 50 Ω 4 Ω Slew Rate Selectable Channel or custom 0 25 V ns 0 7 V ns 1 0 V ns or 1 3 V ns typical Input Threshold Ranges 14 75 V to 14 V VM0 6 75 V to 21 V VM1 Input Threshold Resolution 5 mV Input Threshold Accuracy CVH and CVL 50mV 1 of PV Skew Chan to Chan 3 ns drive and compare Current Source Sink Programmable Channel Range 0 4 mA to 20 mA usable to 24 mA Resolution 10 μA Accuracy 3 of PV 120u...

Page 380: ...board V V and Front Panel DUT_GND Hybrid Connection per Driver Receiver board Connects Front Panel pin to any channel via the Pin Driver electronics User must disable the drive enabled to the channel 40 Ω series impedance 3 MHz bandwidth Auxiliary I O Channels per Driver Receiver board Programmable Level 4 LVTTL 4 ECL 4 Single Ended or Differential AUX I O is bi directional Relay isolation This ra...

Page 381: ...10 5 5 0 2 V CVH max 9 2 6 9 5 12 2 21 8 19 4 V CVH min 12 15 10 5 5 0 2 V CVL max 9 2 6 9 5 12 2 21 8 19 4 V CVL min 12 15 10 5 5 0 2 V CMH max 9 2 6 9 5 12 2 21 8 19 4 V CMH min 12 15 10 5 5 0 2 V CML max 9 2 6 9 5 12 2 21 8 19 4 V CML min 12 15 10 5 5 0 2 V Power Requirements Table D 4 VXI Power Requirements with Front Panel Power Voltage Peak Current Dynamic Current 5 V 3 3 A 330 mA 5 2 V 2 50...

Page 382: ...40 C 5 to 75 5 RH 40 C to 50 C 5 to 55 5 RH Altitude 10 000 ft Cooling Required 10 C Rise 2 DR3s Max 27 4 lps 8 9 mmH2 0 Typ 18 9 lps 4 5 mmH2 0 Front Panel Current Requirements channels unloaded V 3 8 A max 2 9 A typ 21 5 V V 4 3 A max 3 4 A typ 10 5 V MTBF ground benign DR3e 131 656 hours T940 180 885 hours Power Converter 540 040 hours T940 DR3e 66 775 hours T940 DR3e DR3e 44 304 hours Dimensio...

Page 383: ...Model T940 User Manual Publication No 980938 Rev K DR3e Driver Receiver Board D 12 Astronics Test Systems DR3e Signal Description Figure D 5 J200 and J201 Connectors ...

Page 384: ...es AUX7 A 84 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX8 A 86 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX9 A 88 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX9 A 89 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX10 A 90 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX10 A 91 Bi directional General Purpose ECL I...

Page 385: ...IG_GND 12 CH6 62 CH22 13 SIG_GND 63 SIG_GND 14 CH7 64 CH23 15 SIG_GND 65 SIG_GND 16 CH8 66 CH24 17 SIG_GND 67 SIG_GND 18 CH9 68 CH25 19 SIG_GND 69 SIG_GND 20 CH10 70 CH26 21 SIG_GND 71 SIG_GND 22 CH11 72 CH27 23 SIG_GND 73 SIG_GND 24 CH12 74 CH28 25 SIG_GND 75 SIG_GND 26 CH13 76 CH29 27 SIG_GND 77 SIG_GND 28 CH14 78 CH30 29 SIG_GND 79 SIG_GND 30 CH15 80 CH31 31 SIG_GND 81 SIG_GND 32 CH16 82 CH32 3...

Page 386: ...ctional General Purpose I O pin AUX3 B 38 Bi directional General Purpose I O pin AUX4 B 40 Bi directional General Purpose I O pin AUX5 B 42 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX6 B 44 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX7 B 84 Bi directional General Purpose LVTTL I O pin 51 1 Ohm series AUX8 B 86 Bi directional General Purpose LVTTL I O pin 51...

Page 387: ...vices Table D 9 DR3e Pinout by Pin Number DRB Pin No Signal Pin No Signal 1 SIG_GND 51 SIG_GND 2 CH33 52 CH49 3 SIG_GND 53 SIG_GND 4 CH34 54 CH50 5 SIG_GND 55 SIG_GND 6 CH35 56 CH51 7 SIG_GND 57 SIG_GND 8 CH36 58 CH52 9 SIG_GND 59 SIG_GND 10 CH37 60 CH53 11 SIG_GND 61 SIG_GND 12 CH38 62 CH54 13 SIG_GND 63 SIG_GND 14 CH39 64 CH55 15 SIG_GND 65 SIG_GND 16 CH40 66 CH56 17 SIG_GND 67 SIG_GND 18 CH41 6...

Page 388: ... PMODE_B 97 SIG_GND 48 SIG_GND 98 EXTFORCE B 49 GNDREF B 99 SIG_GND 50 MONITOR B 100 DUT_GND B PWR Connector The PWR connector Figure D 6 supplies both positive and negative bias power as well as multi function signals to the DR3e Driver Receiver Board if the external front power option is purchased The DR3e does not require front panel power Figure D 6 Front Panel Optional DR3e PWR Connector When...

Page 389: ...gnal DRA DRA GND 7 Power supply signal return DRA DRA V 8 Negative supply for the DRA Board Pin Electronics devices Calibration Driver Receiver boards are calibrated using the following settings prior to shipment 15 V to 17 V Voltage Mode Power Converter 12 to 12 7 V to 24 V Voltage Mode Power Converter 5 to 15 Table D 11 Calibration Settings DAC Basic Factory stored in EEPROM Driver channel deske...

Page 390: ...ge 31 V to 31 V with an output swing of up to 31 V Relay Isolation on all channel I O Selectable drive current 5 Ω 50 Ω selectable output impedance Over current detection Temperature Monitoring 16 TTL auxiliary channels Front Panel Connectors The front panel of the DR4 Driver Receiver is shown in Chapter 3 no external power connector Block Diagram The DR4 I O Block Diagram Figure E 1 describes the...

Page 391: ... 1 8 SHUTDOWN 1 8 VD2 PROG POSITIVE REGULATOR 2V TO 34V 48V 48V VD2 PROG NEGATIVE REGULATOR 2V TO 34V DAC CONTROL DAC CONTROL CHANNELS TO MUX ADC VOLTAGE TO MUX ADC VOLTAGE TO MUX ADC CHB 49 56 RH RL 49 56 BYPASS 49 56 EN 49 56 SHUTDOWN 49 56 DATA 49 56 HIGH VOLTAGE CHANNELS CHB 33 48 DATA 33 48 RH RL 33 48 BYPASS 33 48 EN 33 48 SHUTDOWN 33 48 16 HIGH VOLTAGE CHANNELS VD3 PROG POSITIVE REGULATOR 2...

Page 392: ...ed to the UUT TEMPMON Real time temperature monitors the PCB junction plane SHUTDOWN These are signals that control the driver output used in Direct Drive mode SEQUENCER A T940 Digital Board Sequencer logic that provides the Stimulus and captures Response data SEQUENCER B T940 Digital Board Sequencer logic that provides the Stimulus and captures Response data 48V This is the common power bus from ...

Page 393: ...Data Sequencer to the programmable output driver EN Channel enable output signal from the Data Sequencer to the solid state switch for tristate OC Over Current signal from the Control logic to the Digital Board Detection of an OC event will disable the channel output in the Series mode OC DETECT Over Current detect from the programmable Driver sense comparator Detection is controlled by Source Sin...

Page 394: ...ction plane VD VD Driver Bias Power from the Programmable Regulators Auxiliary Driver Receiver I O Figure E 3 illustrates the configuration and control of the AUXA 1 8 and the AUXB 1 8 Driver Receiver I Os DB SEQ A 74ABT125 Rt 50Ω 74LVT125 AUXA 1 8 AUXA EN 1 8 AUXA DATA 1 8 AUXA RH 1 8 5V J200 FRONT PANEL R not installed R not installed 74ABT125 Rt 50Ω 74LVT125 AUXB 1 8 AUXB EN 1 8 AUXB DATA 1 8 A...

Page 395: ...uxiliary Response High inputs to the Data Sequencer from the TTL input buffers AUXB 1 8 Eight TTL signals used to input or output test signals DR4Driver Receiver I O OPTIONAL TERMINATION CONFIGURATION The default termination of the TTL AUX I O is a series 50 ohms The pull up and pulldown positions are unpopulated Optional termination configurations can be specified as a Special by contacting the f...

Page 396: ...Current 31V range 50 mA typical Source Sink 20V range 65 mA typical Source Sink Output Impedance Selectable Channel 5 Ω 50 Ω 20 Programmable Drive Current Programmable per group 16 Channel Input Threshold Ranges 0 V to 31 V 15 5 V to 15 5 V 31 V to 0 V Input Threshold levels Dual Threshold Input Threshold granularity Per 2 channels CVH and CVL shared Input Threshold Resolution 20 mV Input Threshol...

Page 397: ...0 C Not controlled 10 C to 30 C 5 to 95 5 RH 30 C to 40 C 5 to 75 5 RH 40 C to 50 C 5 to 55 5 RH Altitude 10 000 ft Cooling Required 10 C Rise 2 DR4s Max tbd lps tbd mmH2 0 Typ tbd lps 4 5 mmH2 0 MTBF ground benign DR4 57 630 hours T940 180 885 hours T940 DR4 43 705 hours EMC Council Directive 89 336 EEC Emission EN61326 1 2006 Class A Immunity EN61326 1 2006 Table 1 Designed to Meet Safety Low Vo...

Page 398: ...l General Purpose TTL I O pin AUX3 A 38 Bi directional General Purpose TTL I O pin AUX4 A 40 Bi directional General Purpose TTL I O pin AUX5 A 42 Bi directional General Purpose TTL I O pin AUX6 A 44 Bi directional General Purpose TTL I O pin AUX7 A 84 Bi directional General Purpose TTL I O pin AUX8 A 86 Bi directional General Purpose TTL I O pin Table E 4 DR4 Pinout by Pin Number DRA Pin No Signal...

Page 399: ...IG_GND 22 CH11 72 NC 23 SIG_GND 73 SIG_GND 24 CH12 74 NC 25 SIG_GND 75 SIG_GND 26 CH13 76 NC 27 SIG_GND 77 SIG_GND 28 CH14 78 NC 29 SIG_GND 79 SIG_GND 30 CH15 80 NC 31 SIG_GND 81 SIG_GND 32 CH16 82 NC 33 SIG_GND 83 SIG_GND 34 AUX1 A 84 AUX7 A 35 SIG_GND 85 SIG_GND 36 AUX2 A 86 AUX8 A 37 SIG_GND 87 SIG_GND 38 AUX3 A 88 NC 39 SIG_GND 89 NC 40 AUX4 A 90 NC 41 SIG_GND 91 NC 42 AUX5 A 92 NC 43 SIG_GND ...

Page 400: ... directional General Purpose TTL I O pin AUX6 B 44 Bi directional General Purpose TTL I O pin AUX7 B 84 Bi directional General Purpose TTL I O pin AUX8 B 86 Bi directional General Purpose TTL I O pin Table E 6 DR4 Pinout by Pin Number DRB Pin No Signal Pin No Signal 1 SIG_GND 51 SIG_GND 2 CH33 52 CH49 3 SIG_GND 53 SIG_GND 4 CH34 54 CH50 5 SIG_GND 55 SIG_GND 6 CH35 56 CH51 7 SIG_GND 57 SIG_GND 8 CH...

Page 401: ... 88 NC 39 SIG_GND 89 NC 40 AUX4 B 90 NC 41 SIG_GND 91 NC 42 AUX5 B 92 NC 43 SIG_GND 93 NC 44 AUX6 B 94 NC 45 SIG_GND 95 MPSIGB 46 PBUT_B 96 BCLK 47 PMODE_B 97 SIG_GND 48 SIG_GND 98 EXTFORCE B 49 NC 99 SIG_GND 50 MONITOR B 100 NC Calibration Driver Receiver boards are calibrated for each range before shipment Field calibration can be performed using Soft Front Panel or API call Table E 7 Calibratio...

Page 402: ...erential RS 422 485 Four TTL Four ECL single ended or differential Front Panel Connectors The front panel of the DR7 Driver Receiver is shown in Chapter 3 Block Diagram This section describes the basic hardware configuration of the DR7 Driver Receiver DRA or DRB The DR7 is comprised of four major logic sections as shown in Figure F 1 Auxiliary Driver Receiver I O DR7 Driver Receiver I O Control Lo...

Page 403: ...8 AUX RH 5 8 AUX DATA 9 12 AUX EN 9 12 AUX RH 9 12 AUX 5 8 AUX 9 12 AUX 9 12 AUX DATA 1 4 AUX EN 1 4 AUX RH 1 4 AUX RL1 CH DATA 1 32 CH EN 1 32 CH RH 1 32 CH RL 1 32 MP SIG CBUS I O CONTROL AUX 1 4 CH 1 32 I O CONTROL I O CONTROL MF SIG AUX 1 4 CH 1 32 Figure F 1 DR7 Driver Receiver Block Diagram Auxiliary Driver Receiver I O Figure F 2 illustrates the configuration and control of AUX5 8 LVTTL and...

Page 404: ...Response High inputs to the Data Sequencer from the LVTTL input buffers AUX RH 9 12 Auxiliary Response High inputs to the Data Sequencer from the ECL input buffers AUX DATA 9 12 Auxiliary active high Data outputs from the Data Sequencer to the ECL output buffers AUX EN 9 12 Auxiliary active low Data outputs from the Data Sequencer to the ECL output buffers EN 9 12 Auxiliary Enable outputs from the...

Page 405: ... drivers EN Channel and auxiliary enable output signals from the Data Sequencer to the RS422 RS485 output drivers RH Response High input signals to the Data Sequencer from the RS422 RS485 input receivers 1 good 1 0 good 0 RL Response Low input signals to the Data Sequencer from the RS422 RS485 input receivers 0 good 0 1 good 1 AUX 1 4 Four positive differential RS422 RS485 signals used to input or...

Page 406: ...loader utility Nonvolatile data serial number assembly revision is stored in an on board EEPROM Signal Descriptions I O CONTROL Signals used to program firmware and NV DATA DR7 Characteristics Table F 1 DR7 Characteristics Description Characteristics Digital I O Type RS 422 485 SN75ALS176 Channels 32 differential per Driver Receiver board Output Voltage VOL 3 0 V max VOH 2 0 V min Differential Inp...

Page 407: ...torage 40 C to 70 C Humidity non condensing 0 C to 10 C Not controlled 10 C to 30 C 5 to 95 5 RH 30 C to 40 C 5 to 75 5 RH 40 C to 50 C 5 to 55 5 RH Altitude 10 000 ft Cooling Required 10 C Rise 1 DR7 Max 1 9 lps 1 mmH2 0 Cooling Required 10 C Rise 2 DR7s Max 2 4 lps 1 mmH2 0 MTBF ground benign DR7 305 905 hours T940 180 885 hours T940 DR7 113 670 hours T940 DR7 DR7 69 804 hours Dimensions 20 x 11...

Page 408: ...eneral Purpose RS 422 485 Positive I O pin AUX2 A 37 Bi directional General Purpose RS 422 485 Negative I O pin AUX3 A 38 Bi directional General Purpose RS 422 485 Positive I O pin AUX3 A 39 Bi directional General Purpose RS 422 485 Negative I O pin AUX4 A 40 Bi directional General Purpose RS 422 485 Positive I O pin AUX4 A 41 Bi directional General Purpose RS 422 485 Negative I O pin AUX5 A 42 Bi...

Page 409: ...2 V AUX12 A 95 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V PBUT A 46 Bi directional Probe Button Input PMODE A 47 Output Probe Support Output BCLK A 96 Output Reserved Table F 4 DR7 Pinout by Pin Number DRA Pin No Signal Pin No Signal 1 SIG_GND 51 SIG_GND 2 CH1 52 CH17 3 CH1 53 CH17 4 CH2 54 CH18 5 CH2 55 CH18 6 CH3 56 CH19 7 CH3 57 CH19 8 CH4 58 CH20 9 CH4 59 CH20 10 CH5 60 CH21 11...

Page 410: ... CH31 32 CH16 82 CH32 33 CH16 83 CH32 34 AUX1 A 84 AUX7 A 35 AUX1 A 85 SIG_GND 36 AUX2 A 86 AUX8 A 37 AUX2 A 87 SIG_GND 38 AUX3 A 88 AUX9 A 39 AUX3 A 89 AUX9 A 40 AUX4 A 90 AUX10 A 41 AUX4 A 91 AUX10 A 42 AUX5 A 92 AUX11 A 43 SIG_GND 93 AUX11 A 44 AUX6 A 94 AUX12 A 45 SIG_GND 95 AUX12 A 46 PBUT_A 96 BCLK A 47 PMODE_A 97 SIG_GND 48 SIG_GND 98 NU 49 NU 99 SIG_GND 50 NU 100 NU ...

Page 411: ...eneral Purpose RS 422 485 Negative I O pin AUX5 B 42 Bi directional General Purpose TTL I O pin 51 1 Ohm series AUX6 B 44 Bi directional General Purpose TTL I O pin 51 1 Ohm series AUX7 B 84 Bi directional General Purpose TTL I O pin 51 1 Ohm series AUX8 B 86 Bi directional General Purpose TTL I O pin 51 1 Ohm series AUX9 B 88 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX9 B 89 Bi...

Page 412: ...table output impedance Auxiliary channels Four TTL with selectable output impedance and resistive input load Four TTL Four ECL single ended or differential Front Panel Connectors The front panel of the DR8 Driver Receiver is shown in Chapter 3 Block Diagram This section describes the basic hardware configuration of the DR8 Driver Receiver DRA or DRB The DR8 is comprised of four major logic section...

Page 413: ... 5 8 AUX RH 5 8 AUX DATA 9 12 AUX EN 9 12 AUX RH 9 12 AUX 5 8 AUX 9 12 AUX 9 12 AUX DATA 1 4 AUX EN 1 4 AUX RH 1 4 AUX RL1 CH DATA 1 32 CH EN 1 32 CH RH 1 32 CH RL 1 32 MP SIG CBUS I O CONTROL AUX 1 4 CH 1 32 I O CONTROL I O CONTROL I O CONTROL MF SIG Figure G 1 DR8 Driver Receiver Block Diagram Auxiliary Driver Receiver I O Figure G 2 illustrates the configuration and control of AUX5 8 TTL and AU...

Page 414: ...s AUX RH 9 12 Auxiliary Response High inputs to the Data Sequencer from the ECL input buffers AUX DATA 9 12 Auxiliary active high Data outputs from the Data Sequencer to the ECL output buffers AUX EN 9 12 Auxiliary active low Data outputs from the Data Sequencer to the ECL output buffers I O CONTROL Signals used to control isolation relays and ECL bipolar differential mode AUX 5 8 Four TTL signals...

Page 415: ...able output signals from the Data Sequencer to the TTL output drivers RH Response High input signals to the Data Sequencer from the TTL input receivers 1 good 1 0 good 0 RL Response Low input signals to the Data Sequencer from the TTL input receivers 0 good 0 1 good 1 AUX 1 4 Four TTL signals used to input or output test signals See Configuring the AUX Channels in Chapter 5 CH 1 32 These are UUT B...

Page 416: ...Table G 1 DR8 Characteristics Description Characteristics Digital I O Type TTL 74LVC2G125 Channels 32 single ended SE per I O board Per channel relay isolation Output Voltage VOL 0 55 V max VOH 3 8 V min Output Drive Current typical Source Sink 32 mA Output Impedance Program selectable per pin Direct or 100 Ω Series 101 Direct or 50 Ω Series 102 Input Voltage VIL 0 8 V max VIH 2 0 V min Input Impe...

Page 417: ...t controlled 10 C to 30 C 5 to 95 5 RH 30 C to 40 C 5 to 75 5 RH 40 C to 50 C 5 to 55 5 RH Altitude 10 000 ft Cooling Required 10 C Rise 2 DR8s Max 4 68 lps 8 9 mmH2 0 Typ 4 60 lps 4 5 mmH2 0 Front Panel Current Requirements NA MTBF ground benign DR8 257 335 hours T940 180 885 hours T940 DR8 106 220 hours T940 DR8 DR8 66 922 hours Dimensions 20 x 114 x 305 mm EMC Council Directive 89 336 EEC Emiss...

Page 418: ...i directional General Purpose TTL I O pin 50 Ω series AUX7 A 84 Bi directional General Purpose TTL I O pin 50 Ω series AUX8 A 86 Bi directional General Purpose TTL I O pin 50 Ω series AUX9 A 88 Bi directional General Purpose ECL I O pin 51 1 Ω to 2V AUX9 A 89 Bi directional General Purpose ECL I O pin 51 1 Ω to 2V AUX10 A 90 Bi directional General Purpose ECL I O pin 51 1 Ω to 2V AUX10 A 91 Bi dir...

Page 419: ...CH21 11 SIG_GND 61 SIG_GND 12 CH6 62 CH22 13 SIG_GND 63 SIG_GND 14 CH7 64 CH23 15 SIG_GND 65 SIG_GND 16 CH8 66 CH24 17 SIG_GND 67 SIG_GND 18 CH9 68 CH25 19 SIG_GND 69 SIG_GND 20 CH10 70 CH26 21 SIG_GND 71 SIG_GND 22 CH11 72 CH27 23 SIG_GND 73 SIG_GND 24 CH12 74 CH28 25 SIG_GND 75 SIG_GND 26 CH13 76 CH29 27 SIG_GND 77 SIG_GND 28 CH14 78 CH30 29 SIG_GND 79 SIG_GND 30 CH15 80 CH31 31 SIG_GND 81 SIG_G...

Page 420: ...se TTL I O pin AUX5 B 42 Bi directional General Purpose TTL I O pin 50 Ohm series AUX6 B 44 Bi directional General Purpose TTL I O pin 50 Ohm series AUX7 B 84 Bi directional General Purpose TTL I O pin 50 Ohm series AUX8 B 86 Bi directional General Purpose TTL I O pin 50 Ohm series AUX9 B 88 Bi directional General Purpose ECL I O pin 51 1 Ohm to 2 V AUX9 B 89 Bi directional General Purpose ECL I O...

Page 421: ...IG_GND 12 CH38 62 CH54 13 SIG_GND 63 SIG_GND 14 CH39 64 CH55 15 SIG_GND 65 SIG_GND 16 CH40 66 CH56 17 SIG_GND 67 SIG_GND 18 CH41 68 CH57 19 SIG_GND 69 SIG_GND 20 CH42 70 CH58 21 SIG_GND 71 SIG_GND 22 CH43 72 CH59 23 SIG_GND 73 SIG_GND 24 CH44 74 CH60 25 SIG_GND 75 SIG_GND 26 CH45 76 CH61 27 SIG_GND 77 SIG_GND 28 CH46 78 CH62 29 SIG_GND 79 SIG_GND 30 CH47 80 CH63 31 SIG_GND 81 SIG_GND 32 CH48 82 CH...

Page 422: ...al ground GND The power pins are not connected to the board Figure G 5 Front Panel PWR Connector When installing the Driver Receiver Board be sure that the correctly marked PWR cable inside the module is connected to its specific board the cable marked DRA for the DRA board and marked DRB for the DRB board Incorrect installation may cause you to be connected to the wrong MFSIG Table G 7 shows the ...

Page 423: ...el T940 User Manual Publication No 980938 Rev K DR8 Driver Receiver Board G 12 Astronics Test Systems Calibration Table G 8 Calibration Settings Inter module timing deskew Static End of cable deskew Static ...

Page 424: ...load with dual commutating voltages Selectable resistive input load 8 choices to a programmed voltage Selectable slew rate 0 25 V ns to 1 5 V ns 12 50 ohm selectable output impedance Over current detection Over voltage detection Auxiliary channels Four LVTTL no relay isolation Front Panel Connectors The front panel of the DR9 Driver Receiver board is shown in Figure H 1 Note The orientations of Pi...

Page 425: ...Model T940 User Manual Publication No 980938 Rev K DR9 Driver Receiver Board H 2 Astronics Test Systems Figure H 1 DR9 Front Panel Connectors ...

Page 426: ...Receiver I O Control Logic Firmware NV Data DR9 DB FRONT PANEL AUXILIARY DRIVER RECEIVER I O DR9 DRIVER RECEIVER I O CONTROL LOGIC FIRMWARE NV DATA AUX DATA 5 8 AUX EN 5 8 AUX RH 5 8 AUX 5 8 CH DATA 1 24 CH EN 1 24 CH RH 1 24 CH RL 1 24 MP SIG CBUS CH 1 24 ACH 1 24 MF SIG OC 1 24 GND_REF TEMPMON EXTFORCE MONITOR INTERRUPT EXTSENSE OVERVOLT V V PC V V DUT_GND EXTSENSE DUT_GND V V I O CONTROL TEMPMO...

Page 427: ...ock Diagram Signal Descriptions AUX EN 5 8 Auxiliary Enable outputs from the Data Sequencer to the LVTTL output buffers AUX DATA 5 8 Auxiliary Data outputs from the Data Sequencer to the LVTTL output buffers AUX RH 5 8 Auxiliary Response High inputs to the Data Sequencer from the LVTTL input buffers I O CONTROL Signals used to control isolation relays AUX 5 8 Four LVTTL signals used to input or ou...

Page 428: ...t the Pin Electronics from potential damage Analog Channel connections have voltage specifications that are far beyond the ability of the DR9 overvoltage detection and protection circuitry to reliably operate Programming an Analog Channel relay opens the associated Digital Channel relay if it is closed There is a 5 ms latency after making the Analog Channel relay connection to ensure that the Digi...

Page 429: ...fore Make MONITOR This is an analog output signal from the Pin Electronics devices which can be used to monitor DAC levels even the Channel I O levels This signal is used with the internal ADC but a buffered version also comes out the Front Panel GND_REF This is the ground reference output signal from the Pin Electronics devices It is used with MONITOR to make accurate ADC measurements A buffered ...

Page 430: ...ntrol Logic Block Diagram Signal Descriptions MP SIG Multi Purpose signal from the data sequencer CBUS An internal Control Bus connecting the digital board to the Driver Receiver board INTERRUPT Real time signal generated from the power and temperature monitor data V PC Positive bias power required for operation of the Pin Electronics devices from the T940 power converter V PC Negative bias power ...

Page 431: ...ts to the V rails DUT_GND Either the front panel DUT_GND signal or SIG GND EXTFORCE Pin electronics signal used for calibration EXTSENSE Pin electronics signal used for calibration TEMPMON Real time temperature monitors for the pin electronics Firmware NV Data The Control Logic firmware is loaded via a serial PROM on power up or VXI Reset The firmware is field upgradeable using our supplied loader...

Page 432: ...e 0 4 mA to 20 mA usable to 24 mA Resolution 10 μA Accuracy 3 of PV 120uA Commutating Voltage Vcom CMH and CML Range same as driver Resolution 5 mV Accuracy 50mV 1 of PV Over Current Alarm IAH and IAL Range 800 mA Resolution 30 μA Accuracy 50mA 1 of PV Resistive Loads Selectable Channel 140 Ω to 1 KΩ 8 selections to Vcom Accuracy 30 PMU capability Voltage Range Resolution Accuracy same as driver D...

Page 433: ...operation Hybrid Channel Relay Connection per channel 200 V Adjacent Channels must be 0 V for 200 V or 0 V or below for 200 V Hybrid Channel Relay Isolation 32 db 200 MHz 29 db 100 MHz Hybrid Channel Relay Insertion Loss Insertion loss 0 40 db 200 MHz Insertion loss 0 15 db 100 MHz Auxiliary I O Channels per Driver Receiver board LVTTL 4 fixed 50 Ω series terminations for calibration support This ...

Page 434: ...5 12 2 21 8 19 4 V CVH min 12 15 10 5 5 0 2 V CVL max 9 2 6 9 5 12 2 21 8 19 4 V CVL min 12 15 10 5 5 0 2 V CMH max 9 2 6 9 5 12 2 21 8 19 4 V CMH min 12 15 10 5 5 0 2 V CML max 9 2 6 9 5 12 2 21 8 19 4 V CML min 12 15 10 5 5 0 2 V Power Requirements Table H 4 DR9 Power Requirements not including Power Converter power consumption Voltage Peak Current Dynamic Current 12V 16 9 mA 15 mA 12V 18 1 mA 1...

Page 435: ... Cooling Required 10 C Rise 2 DR9s Max 19 5 lps 4 6 mmH2 0 Typ 13 lps 2 2 mmH2 0 Front Panel Current Requirements channels unloaded per DR3 V 3 8 A max 2 9 A typ 21 5 V V 4 3 A max 3 4 A typ 10 5 V MTBF ground benign DR9 145 933 hours T940 180 885 hours Power Converter 540 040 hours T940 DR9 70 261 hours T940 DR9 DR9 47 427 hours Dimensions 23 x 114 x 294 mm EMC Council Directive 89 336 EEC Emissi...

Page 436: ...l Astronics Test Systems DR9 Driver Receiver Board H 13 DR9 Signal Description Figure H 6 DR9 J1A J1B J2A J2B J3A and J3B Signal Connectors Pin 1 Pin 1 Pin 1 Note that connectors J1A and J1B have been rotated 180 and the location of Pin 1 is as shown ...

Page 437: ...d SIG_GND Various Signal Ground reference Refer to Figure H 6 and Tables H 6 through H 8 Table H 6 J3A Connector Pinout by Pin Number Connector Pin Signal Connector Pin Signal Resource A or B 1 GND 2 ACH 33 B 3 GND 4 ACH 34 B 5 GND 6 ACH 35 B 7 GND 8 ACH 36 B 9 GND 10 ACH 37 B 11 GND 12 ACH 38 B 13 GND 14 ACH 39 B 15 GND 16 ACH 40 B 17 GND 18 ACH 41 B 19 GND 20 ACH 42 B 21 GND 22 ACH 43 B 23 GND 2...

Page 438: ...ACH 3 A 23 GND 24 ACH 4 A 25 GND 26 ACH 5 A 27 GND 28 ACH 6 A 29 GND 30 ACH 7 A 31 GND 32 ACH 8 A 33 NC 34 NC Table H 8 J1A Connector Pinout by Pin Number Connector Pin Signal Connector Pin Signal Resource A or B 1 GND 2 ACH 24 A 3 GND 4 ACH 23 A 5 GND 6 ACH 22 A 7 GND 8 ACH 21 A 9 GND 10 ACH 20 A 11 GND 12 ACH 19 A 13 GND 14 ACH 18 A 15 GND 16 ACH 17 A 17 GND 18 ACH 16 A 19 GND 20 ACH 15 A 21 GND...

Page 439: ...l or signal ground SIG_GND Various Signal Ground reference Refer to Figure H 6 and Tables H 10 through H 12 Table H 10 J3B Connector Pinout by Pin Number Connector Pin Signal Connector Pin Signal Resource A or B 1 GND 2 CH 33 B 3 GND 4 CH 34 B 5 GND 6 CH 35 B 7 GND 8 CH 36 B 9 GND 10 CH 37 B 11 GND 12 CH 38 B 13 GND 14 CH 39 B 15 GND 16 CH 40 B 17 GND 18 CH 41 B 19 GND 20 CH 42 B 21 GND 22 CH 43 B...

Page 440: ... GND 22 CH 3 A 23 GND 24 CH 4 A 25 GND 26 CH 5 A 27 GND 28 CH 6 A 29 GND 30 CH 7 A 31 GND 32 CH 8 A 33 NC 34 NC Table H 12 J1B Connector Pinout by Pin Number Connector Pin Signal Connector Pin Signal Resource A or B 1 GND 2 CH 24 A 3 GND 4 CH 23 A 5 GND 6 CH 22 A 7 GND 8 CH 21 A 9 GND 10 CH 20 A 11 GND 12 CH 19 A 13 GND 14 CH 18 A 15 GND 16 CH 17 A 17 GND 18 CH 16 A 19 GND 20 CH 15 A 21 GND 22 CH ...

Page 441: ...al General Purpose LVTTL I O pin 50 Ohm series PROBE MODE A 9 Output Probe Support Output BCLK A 11 Output Serial Clock PBUT A 13 Bi directional Probe Button Input MPSIG A 15 Output Multi purpose Signal MONITOR A 17 Output Monitor signal from the Pin Electronics devices Note Only one channel can be selected at a time EXTFORCE A 19 Input External Force routed to all of the Pin Electronics devices u...

Page 442: ...f the Pin Electronics devices used to calibrate the instrument to an external standard GND 2 20 Even Ground Calibration Driver Receiver boards are calibrated using the following settings prior to shipment 15 V to 17 V Voltage Mode Power Converter 12 to 12 7 V to 24 V Voltage Mode Power Converter 5 to 15 DAC Basic Factory stored in EEPROM Driver channel deskew Factory stored in EEPROM ADC Monitor F...

Page 443: ...Model T940 User Manual Publication No 980938 Rev K DR9 Driver Receiver Board H 20 Astronics Test Systems This page was left intentionally blank ...

Page 444: ...etection per byte 0 20V Programmable Over current detection per byte 0 1A External Probe Support Auxiliary I O channels Six programmable Two are dedicated for the external probe when used Two LVTTL One is dedicated for the external probe when used Three ECL single ended or differential Four LVTTL or SE ECL Four LVTTL or ECL single ended or differential See Figure I 1 for a front panel illustration...

Page 445: ...Model T940 User Manual Publication No 980938 Rev K UR14 Driver Receiver Board I 2 Astronics Test Systems Figure I 1 UR14 Front Panel ...

Page 446: ... 9 12 A AUX 5 9 A AUX 6 10 A AUX 7 11 A AUX 8 12 A EXTSENSE TEMPMON OVERVOLT TEMPMON OVERVOLT DUT GND ADC VOLTAGE TEMPERATURE MONITORING DUT_GND V V PC V V V V OVERVOLT TEMPMON OVERVOLT DUT GND V V SATURN TEMP EXTSENSE EXTSENSE I O CONTROL OCREF 1 4 INREF 1 4 OCREF 1 4 DB FRONT PANEL INREF 1 4 EXTSENSE AUX 9 11 B AUX 5 8 B AUX 9 11 B AUX DATA3A AUX EN3A I O CONTROL Figure I 2 UR14 Driver Receiver ...

Page 447: ...lity UR14 calibration data is stored in an on board EEPROM and is loaded initialization of the T940 unit UR14 power on time is stored for reference using an on board timer Auxiliary Driver and Receiver I O ECL LVTTL The Auxiliary Driver and Receiver I O ECL LVTTL block diagram Figure H 3 illustrates the configuration and control of Auxiliary ECL LVTTL Driver Receivers on the UR14 UR14 33Ω 2V MC100...

Page 448: ...L output buffers AUX EN 9 12 A Auxiliary Data outputs from the Data Sequencer to the negative side ECL output buffers AUX DATA 5 8 A Auxiliary Data outputs from the Data Sequencer to the LVTTL output buffers AUX EN 5 8 A Auxiliary Enable outputs from the Data Sequencer to the LVTTL output buffer AUX RH 5 8 A Auxiliary Response Input to the Data Sequencer from the LVTTL input buffers I O CONTROL Co...

Page 449: ...L requires no Sequencer assignment changes Signal Descriptions Figure I 4 AUX RH 5 8 B Auxiliary Response Inputs to the Data Sequencer from the LVTTL or ECL input buffers AUX EN 5 8 B Auxiliary Enable outputs from the Data Sequencer to the LVTTL output buffers AUX DATA 5 8 B Auxiliary Data outputs from the Data Sequencer to the ECL and LVTTL output buffers I O CONTROL Control Logic signals to cont...

Page 450: ...sponse Inputs to the Data Sequencer from the ECL input buffers AUX DATA 9 11 BAuxiliary Data outputs from the Data Sequencer to the positive side ECL output buffers AUX EN 9 11 B Auxiliary Data outputs from the Data Sequencer to the negative side ECL output buffers AUX RH12B Auxiliary Response Input to the Data Sequencer from the AUX12 B ECL input buffers AUX DATA12B Auxiliary Data output from the...

Page 451: ...Ω DVH DVL CVH CVL PROBE_CAL PROBE OUT 12VF PROBE POWER UR14 CAL REFERENCES EXTSENSE PBUT PROB MODE BCLK 12VF NC NO PROBE INPUT DC CALIBRATION AUX EN4A AUX DATA4A 33Ω Rt 50Ω AUX RH4A 74LVT125 PROBE DETECT I O CONTROL DSA GNDREF AUX1 A AUX2 A PROBE COMP NC DUT_GND I O CONTROL I O CONTROL ALL RELAYS CONTROL LOGIC FRONT PANEL AUX4 A Figure I 6 Probe I O Block Diagram Signal Descriptions Figure I 6 AUX...

Page 452: ...he Pin Driver Logic Any DUT_GND offsets are applied to the external probe module When not used with the external probe this signal comes from the UUT and can be used to offset the reference levels up to 3 V Excursions of DUT_GND beyond 390 mV with respect to signal ground yields a GND FAULT signal DUT_GND can be used to apply this offset to the probe module input PROBE OUT Signal path that can be ...

Page 453: ...VCom Hi I Source I Sink VCom Lo DAC I O CONTROL AUX1 4 B DUT_GND PIN ELECTRONICS CVH 50Ω CONTROL LOGIC EXTSENSE V V CONTROL LOGIC MONITOR GND_REF EXTFORCE TEMPMON TEMP Figure I 7 Programmable Driver and Receiver I O Signal Descriptions Figure I 7 DATA Auxiliary data output signals from the Data Sequencer to the programmable output drivers EN Auxiliary enable output signals from the Data Sequencer ...

Page 454: ... the ground reference output signal from the Pin Electronics devices It is used with MONITOR to make accurate ADC measurements A buffered version also comes out the Front Panel EXTFORCE External Force is an analog I O signal which is connected to all of the Pin Electronics devices and can be used to force a level on the output of the driver It may also be used to monitor a channel s state EXTFORCE...

Page 455: ...he Data Sequencer to the Open Collector Driver OC 33 64 Sequencer B Channel Over Current detect signals to the Data Sequencer from Open Collector Driver over current detect comparator Depending on Sequencer B settings a detected over current can shut off just the channel or all channels CH 1 32 Data I O Open Collector Channels These channels can be used with high voltage inductive loads The 5V pul...

Page 456: ...1 1 1 GND ADC_IN GND LBUS LBUS REAL TIME VOLTAGE MONITORING PRECISION VOLTAGE REFERENCES 10VREF 5VREF 10VREF 5VREF REAL TIME TEMPERATURE MONITORING THRESHOLDS PIN DRIVER TEMP TEMP ALARMS REAL TIME PIN ELECTRONICS OVERVOLTAGE DETECTION OVH 1 6 OVERVOLTAGE ALARM OVL 1 6 6 EXTSENSE VOLTAGE ALARMS 6 6 UR14 Logic DUT_GND BPV BPV 1 1 1 PIN DRIVERS PIN ELECTRONICS SOLID STATE SWITCHES 1 V V AUX A1 AUX A2...

Page 457: ...e Pin Driver electronics channel I O and provide to the real time Pin Electronics Overvoltage Detection circuitry with levels that indicate an Overvoltage condition OVERVOLTAGE ALARMS The output from the monitoring circuitry that goes to the UR14 LOGIC VOLTAGE ALARMS Real time over voltage which monitors the PIN ELECTRONICS Driver and Receivers to protect the UR14 board DUT_GND This signal comes f...

Page 458: ...his control logic provides facilitates UR14 functions including access to the Pin Electronics devices Temperature Monitoring programming Voltage Over voltage and Over Temperature detection Firmware and Calibration Storage The UR14 Control Logic FPGA firmware is loaded via a serial PROM on power up or VXI Reset The firmware is field upgradeable using our supplied loader utility UR14 calibration dat...

Page 459: ... circuitry and PROBE and CAL BNC connections PROBE COMP AUX4 A Output to the external probe module to control the contact detect relay When not used with the probe it can be used as an I O signal PROBE OUT Signal path that can be used to adjust the compensation of the external probe Note that this connection is not on the probe connector PROBE IN Input signal from the external probe When not used ...

Page 460: ...z probe assembly MODEL PM6139 that includes a push button and LED that connect to the External Probe Module via an included cable and connector CONNECT SWITCH is a push button on the PROBE that is used to signal a sequence start to the T940 Sequencer via PBUT CONNECT LED is an LED on the PROBE that when lighted indicates contact detection PROBE DETECT this input detects the presence of an external...

Page 461: ...ms External Probe Module The T940 UR14 is specifically configured to support the external probe module There are two module types a Flush Mounted PCB Assembly Figure I 11 and a Right Angle PCB Assembly Figure I 12 Figure I 11 External Probe Module Flush Mount Figure I 12 External Probe Module Right Angle ...

Page 462: ...dule Table I 1 External Probe Module Characteristics Description Notes Interfaces to legacy panels Two types of assemblies Can mount vertically or horizontally Provides a BNC connector for the Probe with and isolation provision when mounted to the customer panel Provides a BNC connector for calibrating the Probe at the Probe Tip Compensation and DC Calibration Utilizes a cable to connect the Probe...

Page 463: ... the pushbutton signal is received Footswitch signaling simply requires tapping into the Probe Aux connector Supports dual threshold detection Via the UR14 AUX1 A input Utilizes Window 4 for Probe Data capturing Implemented in the T940 DB Sequencer see relevant manual section Detectable states 34 Provided in the T940 DB Sequencer Provides Capture Learn and Expect Compare of Probe input Provided in...

Page 464: ... 1 per byte OC detect levels 16 selections in Amps 0 06 0 12 0 19 0 25 0 31 0 37 0 44 0 5 0 56 0 63 0 69 0 75 0 81 0 87 0 94 1 Input Sink Current Up to 1 A per channel or 1 A max per byte On board pull up 1 kΩ to 5 V default allows each channel to be used as low speed TTL Output Impedance 520 mΩ per channel Input References 4 input references INREF 1 Channels 1 8 INREF 2 Channels 9 16 INREF 3 Chan...

Page 465: ...to 14 V VM0 6 75 V to 21 V VM1 Input Threshold Resolution 5 mV Input Threshold Accuracy 50mV 1 of PV Current Source Sink Programmable Channel Range 0 4 mA to 20 mA usable to 24 mA Resolution 10 μA Accuracy 3 of PV 120uA Commutating Voltage Vcom CMH and CML Range same as driver Resolution 5 mV Accuracy 50mV 1 of PV Over Current Alarm IAH and IAL Range 800 mA Resolution 30 μA Accuracy 50mA 1 of PV R...

Page 466: ...e I 4 Programmable AUX I O Min Max Levels Front Panel Level Min Max Units DVH V 5 V 3 V DVL V 4 V 7 V CVH V 2 V 7 V CVL V 2 V 7 V Vcom High CMH V 2 V 7 V Vcom Low CML V 2 V 7 V The following table lists the min and max levels based on the power converter type 1 or 3 setting Table I 5 Programmable AUX I O Min Max Levels Power Converter Type 1 or 3 Level Power Converter Setting Units 12 to 12 15 to ...

Page 467: ...odule entry below PROBE_OUT Connects to PROBE_IN for external probe compensation PROBE_DETECT LVTTL input used to detect the presence of the external probe module 12V 12V Low current power for external probe support Max current 200 mA PROBE MODULE CHARACTERISTICS Table I 8 Probe Module Characteristics Description Characteristics Probe Tip Characteristics Input capacitance 20 pF Input Impedance 10 ...

Page 468: ... can get access to the trim pot PROBE CALIBRATION FIELD Utilizes AUX A 2 provided by the D R board to provide a reference signal on the Probe Module s calibration connector which will be used for Probe Compensation Calibration and DC Timing Calibration to the Probe tip MINIMUM DETECTABLE PULSE WIDTH 10 ns BUFFERED PROBE OUTPUT Provided on the UR14 as PROBE OUT Output range Same as input from the P...

Page 469: ...0 Ω terminated ECL is parallel terminated 50 Ω to 2 V AUX 9 12 A Negative side of differential ECL AUX 9 12 A used when these channels are configured as differential ECL Parallel terminated 50 Ω to 2 V Bi directional General purpose I O 50 MHz data rate I O Per channel relay isolation AUX 1 4 B Programmable AUX 5 8 B LVTTL or ECL These channels are a programmable selection of either LVTTL or SE EC...

Page 470: ... I 11 Environmental Temperature Operating 0 C 45 C Storage 40 C 70 C Humidity 5 to 95 Altitude 10 000 ft Cooling Required 10 C Rise 2 UR14s Max 14 4 lps 2 8 mmH20 Typ 10 4 lps 1 6 mmH20 MTBF ground benign UR14 179 889 hours T940 180 855 hours Power Converter 540 040 hours T940 UR14 77 279 hours Dimensions 20 x 114 x 305 mm EMC Council Directive 89 336 EEC Emission EN61326 1 2006 Class A Immunity E...

Page 471: ...H8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 GND GND AUX3 A NC PROBE OUT AUX 7 11 A NC NC AUX 6 10 A AUX 5 9 A DUT_GND 12V 12V DUT_GND GND_REF BCLK PBUT PROBE MODE PROBE COMP PROBE DETECT GND GND PROBE_CAL PROBE_IN CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 NC NC NC NC AUX4 B AUX3 B AUX2 B AUX1 B NC NC NC NC AUX8 B AUX7 B AUX6 B AUX5 B GND NC NC NC NC NC NC ADC_IN Pin 7 NC NC GND VEXT VEXT AUX9A AUX10 A AUX11 A AU...

Page 472: ...ntial ECL AUX 9 12 A used when these channels are configured as differential ECL AUX 5 8 B LVTTL or ECL these channels are a programmable selection of either LVTTL or SE ECL AUX 9 11 B AUX 9 11 B SE ECL or Differential ECL bi directional general purpose I O PROBE OUT Probe Support External probe module probe compensation test point This is a direct connection to PROBE_IN PROBE MODE PBUT BCLK PROBE...

Page 473: ...ctor Pin Signal 1 GND 2 CH32 3 GND 4 CH31 5 GND 6 CH30 7 GND 8 CH29 9 GND 10 CH28 11 GND 12 CH27 13 GND 14 CH26 15 GND 16 CH25 17 GND 18 NC 19 GND 20 NC 21 GND 22 NC 23 GND 24 NC 25 GND 26 AUX4 B 27 GND 28 AUX3 B 29 GND 30 AUX2 B 31 GND 32 AUX1 B 33 GND 34 NC 35 GND 36 NC 37 GND 38 NC 39 GND 40 NC 41 GND 42 AUX8 B 43 GND 44 AUX7 B 45 GND 46 AUX6 B 47 GND 48 AUX5 B 49 GND 50 GND ...

Page 474: ...6 CH17 17 GND 18 CH16 19 GND 20 CH15 21 GND 22 CH14 23 GND 24 CH13 25 GND 26 CH12 27 GND 28 CH11 29 GND 30 CH10 31 GND 32 CH9 33 GND 34 CH8 35 GND 36 CH7 37 GND 38 CH6 39 GND 40 CH5 4 GND 42 CH4 13 GND 44 CH3 45 GND 46 CH2 47 GND 48 CH1 49 GND 50 GND Table I 15 J2A Connector Pinout by Pin Number Connector Pin Signal Connector Pin Signal 1 GND 2 DUT_GND 3 GND 4 AUX 5 9 A 5 GND 6 AUX 6 10 A 7 GND 8 ...

Page 475: ...e I 17 J1A Connector Pinout by Pin Number Connector Pin Signal Connector Pin Signal 1 GND 2 PROBE_IN 3 GND 4 PROBE_CAL 5 GND 6 GND 7 GND 8 GND 9 GND 10 PROBE_DETECT 11 GND 12 AUX4 A 13 GND 14 PMODE 15 GND 16 PBUT 17 GND 18 BCLK 19 GND 20 GND_REF 21 GND 22 DUT_GND 23 GND 24 12V 25 GND 26 12V Table I 18 J1B Connector Pinout by Pin Number Connector Pin Signal Connector Pin Signal 1 GND 2 AUX 8 12 A 3...

Page 476: ...5 A 1 Bi directional General Purpose LVTTL I O pin 50 Ohm series AUX6 A 3 Bi directional General Purpose LVTTL I O pin 50 Ohm series AUX7 A 5 Bi directional General Purpose LVTTL I O pin 50 Ohm series AUX8 A 7 Bi directional General Purpose LVTTL I O pin 50 Ohm series PROBE MODE A 9 Output Probe Support Output BCLK A 11 Output Serial Clock PBUT A 13 Bi directional Probe Button Input MPSIG A 15 Out...

Page 477: ...Monitor signal from the Pin Electronics devices Note Only one channel can be selected at a time EXTFORCE B 19 Input External Force routed to all of the Pin Electronics devices GND 2 20 Even Ground Calibration Driver Receiver boards are calibrated using the following settings prior to shipment 15 V to 17 V Voltage Mode Power Converter 12 to 12 7 V to 24 V Voltage Mode Power Converter 5 to 15 DAC Ba...

Page 478: ...four There are two types of VXI TRG inputs TTL and ECL The TTL input will be used as the timing reference with adjustment values provided for the ECL input Similarly the External outputs include the AUX and TRG outputs There are five types of AUX outputs Programmable LVTTL ECL LVDS and 422 485 The LVTTL AUX output will be used as the timing reference with adjustment values provided for the other t...

Page 479: ...talled Other VXI modules installed in the same chassis may further aggravate the recovery time The leading edge for the TTLTRG Bus is a falling edge TRG Output Timing Adjustments TTLTRG Bus timing reference to the leading edge ECLTRG Bus 1 ns faster AUX Input to TRG AUX LVTTL to TTLTRG Bus 16 ns TRG Input to AUX Output TTLTRG to AUX LVTTL 15 ns LE DRS Timing Adjustments Independent timing referenc...

Page 480: ...ion to this there is an additional amount of time up to the period of the master clock before the master clock appears to stop FE An internal signal External Pause Phase Resume to CLK Resume There are no clocked elements in this path AUX LVTTL to NOT CLK_Stop 22 ns To addition to this there is an additional amount of time up to one full period of the master clock before the master clock actually r...

Page 481: ...respect to the last T0CLK of the Idle step Add to x Linked or VXI Local Bus adjustments External Stop Setup Time to T0CLK In For a 10 master clock pattern period AUX LVTTL to T0CLK 70 ns max 500 MHz master clock AUX LVTTL to T0CLK 222 ns max 100 MHz master clock x 2n 70 ns x 10n 222 ns Thus n 19 x 32 ns of fixed delay n is composed of a 9 master clock intrinsic delay plus the period of the pattern...

Page 482: ...quipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentation Artisan Scientific Corporation dba Artisan Technology Group is not an affiliate representative or authorized distributor for any manufacturer listed herein We re here to make your life easier How...

Reviews:

No comments