Publication No. 980938 Rev. K
Model T940 User Manual
Astronics Test Systems
Advanced Topics 8-31
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High
o
Low
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Rising Edge
o
Falling Edge
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Pause Test 1-2 Resume Sources (static selection):
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Any Aux. Input (1 of 12)
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Any TTLTRG Bus input (1 of 8)
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Either ECL TRG Bus input (1 of 2)
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Channel Test 1 (master channel test)
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Phase Test 1-4 Resume Sources (static selection):
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Any Aux. Input (1 of 12)
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Any TTLTRG Bus input (1 of 8)
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Either ECL TRG Bus input (1 of 2)
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Channel Test 1 (master channel test)
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Pause Test 1-2 or Phase Test 1-4 Resume Conditions (static selection):
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High
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Low
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Rising Edge
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Falling Edge
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Pause Resume Options (settable in each Seq. Step)
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None
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Pattern Delay Timer 1 (used to Resume after a fixed delay)
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Pattern Delay Timer 2 (used to Resume after a fixed delay)
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Pattern Timeout Timer
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Pattern Delay/Timeout Timer (static settings):
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Range: ~20 ns to ~43s
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Resolution: 10ns
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Pause Timing Considerations:
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An external signal used to initiate the pause must occur in a timely
manner with respect to the Primary Sequencer. The “pause” signal
must be provided ~10 Master Clocks and 40-60ns before the desired
pausing point (to be refined).
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Using a Phase edge to pause will have less delay but will still require
a few Master Clocks which may vary depending on the placement of
the Phase edge (to be refined)
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Pause Edge Test 1-2 Clear options (static selection):