Model T940 User Manual
Publication No. 980938 Rev. K
Advanced Topics 8-30
Astronics Test Systems
resumes (a Resume is not needed in this case). Thus the actual duration of
the Halt will most likely be longer than the duration of the System Clutch.
Halt Notes:
•
When Halted, the CPU may access the Data, Record and Probe
memories.
•
A Resume will be ignored while memory access is granted.
•
An external Halt can only halt on a Pattern.
•
When the timing requirements are not met for completing the capture of
the response data prior to the Halt, the response data and related error
counting/logging will be corrupted. See the Jumping, Halting, Counting
and Logging on Pass/Fail section for the detailed timing requirements and
additional information.
Pause Operations:
•
A Pause operation is defined within a Sequence Step. Thus it can be
constrained to occur only at particular times during the Sequence.
•
Pause Test Condition Choices (settable in each Seq. Step):
o
None
o
Always
o
Pause Test 1 True or Not True
o
Pause Test 2 True or Not True
o
Phase 1 Rising Edge (RE)
o
Phase 1 Falling Edge (FE)
o
Phase 2 RE
o
Phase 2 FE
o
Phase 3 RE
o
Phase 3 FE
o
Phase 4 RE
o
Phase 4 FE
•
Pause Test 1-2 Sources (static selection):
o
None
o
Any Aux. Input (1 of 12)
o
Any TTLTRG Bus input (1 of 8)
o
Either ECL TRG Bus input (1 of 2)
o
Channel Test 1 (master channel test)
•
Pause Test 1-2 Conditions (static selection):