AT32F413
Series Reference Manual
2022.06.27
Page 276
Rev 2.00
19.4.4 Data management
At the end of the conversion of the ordinary group, the converted value is stored in the ADC_ODT register.
Once the preempted group conversion ends, the converted data of the preempted group is stored in the
ADC_PDTx register.
19.4.4.1 Data alignment
DTALIGN bit in the ADC_CTRL2 register selects the alignment of data (right-aligned or left-aligned).
Apart from this, the converted data of the preempted group is decreased by the offset written in the
ADC_PCDTOx register. Thus the result may be a negative value, marked by SIGN, as shown in
Figure 19-8
Data alignment
SIGN
SIGN
SIGN
SIGN
DT[11]
DT[10]
DT[9]
DT[8]
DT[7]
DT[6]
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
SIGN
DT[11]
DT[10]
DT[9]
DT[8]
DT[7]
DT[6]
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
0
0
0
0
0
0
0
DT[11]
DT[10]
DT[9]
DT[8]
DT[7]
DT[6]
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
DT[11]
DT[10]
DT[9]
DT[8]
DT[7]
DT[6]
DT[5]
DT[4]
DT[3]
DT[2]
DT[1]
DT[0]
0
0
0
0
Preempted channel data 12 bits
Right-alignment
Ordinary channel data 12 bits
Right-alignment
Left-alignment
Left-alignment
19.4.4.2 Data read
Read access to the ADC_ODT register using CPU or DMA gets the converted data of the ordinary group.
Read access to the ADC_PDTx register using CPU gets the converted data of the preempted group.
When the OCDMAEN is set in the ADC_CTRL2 register, the ADC will issue DMA requests each time
when the ADC_OTD register is updated.
ADC1 has its own DMA channels. In Master/Slave mode, the ADC2 as slave can be read by DMA
through the master ADC1.
19.4.5 Voltage monitor
OCVMEN bit or PCVMEN bit in the ADC_CTRL1 register is used to enable voltage monitoring. The
VMOR bit will be set if the converted result is outside the high threshold (ADC_VMHB register) or is less
than the low threshold (ADC_VMLB register).
VMSGEN bit in the ADC_CTRL1 register is used to enable voltage monitor on either a single specific
channel or all the channels. The VMCSEL bit is used to select the specific channel that requires voltage
monitoring.
Voltage monitoring is based on the comparison result between the original converted data and the 12-
bit voltage monitor boundary register, irrespective of the PCDTOx and DTALIGN bits.
19.4.6 Status flag and interrupts
Each of the ADCs has its dedicated ADCx_STS reisters, that is, OCCS (ordinary channel conversion
start flag), PCCS (preempted channel conversion start flag), PCCE (preempted channel conversion end
flag), CCE (channel conversion end flag) and VMOR (voltage monitor out of range).
PCCE, CCE and VMOR have their respective interrupt enable bits. Once the interrupt bits are enabled,
the corresponding flag is set and an interrupt is sent to CPU. ADC1 shares an interrupt vector with ADC2.