AT32F413
Series Reference Manual
2022.06.27
Page 191
Rev 2.00
shows the example of clearing CxORAW signal. When the EXT input is high, the CxORAW
signal, which was originally high, is driven low; when the EXT is low, the CxORAW signal outputs the
corresponding level according to the comparison result between the counter value and CxDT value.
Figure 14-20
Clearing CxORAW(PWM mode A) by EXT input
0
1
2
3
4
5
6
7
8
9
A
B
C
D
0
1
2
3
COUNTER
CxOSEN
7
CxDT
EXT
CxORAW
14.1.3.5 TMR synchronization
The timers are linked together internnaly for timer synchronization. Master timer is selected by setting
the PTOS[2: 0] bit; Slave timer is selected by setting the SMSEL[2: 0] bit.
Slave mode include:
Slave mode: Reset mode
The counter and its prescaler can be reset by a selected trigger signal. An overflow event
is generated when OVFS=0.
Figure 14-21
Example of reset mode
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
COUNTER
30
31
32
0
...
PR[15:0]
CI1F1
TMR_CLK
0
DIV[15:0]
32
101
STIS[2
：
0]
OVFIF
TRGIF
100
SMSEL[2
：
0]
Slave mode: Suspend mode
In this mode, the counter is controlled by a selected trigger input. The counter starts counting when the
trigger input is high and stops as soon as the trigger input is low.