AT32F413
Series Reference Manual
2022.06.27
Page 52
Rev 2.00
1: HEXT clock is used as PLL entry clock
Bit 28
Bit 15: 14
ADCDIV
0x0
rw
ADC division
PCLK division is used as ADC clock.
000: PCLK divided by 2 to be ADC clock
001: PCLK divided by 4 to be ADC clock
010: PCLK divided by 6 to be ADC clock
011: PCLK divided by 8 to be ADC clock
100: PCLK divided by 2 to be ADC clock
101: PCLK divided by 12 to be ADC clock
110: PCLK divided by 8 to be ADC clock
111: PCLK divided by 16 to be ADC clock
Bit 13: 11
APB2DIV
0x0
rw
APB2 division
HCLK frequency division is used as APB2 clock.
0xx: HCLK is not divided
100: HCLK is divided by 2
101: HCLK is divided by 4
110: HCLK is divided by 8
111: HCLK is divided by 16
Note: These bit must be configured by software to ensure
that the APB2 clock frequency is less than 100 MHz.
Bit 10: 8
APB1DIV
0x0
rw
APB1 division
HCLK frequency division is used as APB1 clock.
0xx: HCLK is not divided
100: HCLK is divided by 2
101: HCLK is divided by 4
110: HCLK is divided by 8
111: HCLK is divided by 16
Note: These bit must be configured by software to ensure
that the APB1 clock frequency is less than 100 MHz.
Bit 7: 4
AHBDIV
0x0
rw
AHB division
The divided SCLK is used as AHB clock.
0xxx: SCLK is not divided
1000: SCLK is divided by 2
1001: SCLK is divided by 4
1010: SCLK is divided by 8
1011: SCLK is divided by 16
1100: SCLK is divided by 64
1101: SCLK is divided by 128
1110: SCLK is divided by 256
1111: SCLK is divided by 512
Note: Prefetch buffer must be enabled when the AHB
prescaler factor is greater than 1.
Bit 3: 2
SCLKSTS
0x0
ro
System clock select status
00: HICK
01: HEXT
10: PLL
11: Reserved, default value.
Bit 1: 0
SCLKSEL
0x0
rw
System clock select
00: HICK
01: HEXT
10: PLL
11: Reserved, default value.