AT32F413
Series Reference Manual
2022.06.27
Page 126
Rev 2.00
7-bit address mode:
1.
Generate a Start condition (GENSTART=1)
2.
EV1: Start condition is ready (STARTF=1). Read STS1 by software and write the address to DT
register.
3.
EV2: Address is matched successfully (ADDR7F=1). Reading STS1 and then STS2 clears the
ADDR7F bit. At this point, the master enters transmit stage, and both DT register and internal shift
regiser are empty. The TDBE bit is set 1 by hardware.
4.
EV3: When the data is written to the DT register, it is directly moved to the shift register and the
SCL bus is released. The TDBE bit is still set 1 at this time.
5.
EV4: The DT register remains empty but the shift register is not. Writing to the DT register clears
the TDBE bit.
6.
The TDBE bit is set only after the second-to-last byte is sent.
7.
EV5: TDC=1 indicates that the byte transmission is complete. The master sends a Stop condition
(STOPF=1). The TDBE bit and TDC bit are cleared automatically by hardware.
8.
End of communication.
10-bit address mode:
1.
Generate Start condition (GENSTART=1)
2.
EV1: Start condition is ready (STARTF=1). Read STS1 and write the address to DT register.
3.
EV6: 10-bit address head sequence is sent. Reading STS1 and writing to DT register clears the
ADDRHF bit.
4.
EV2: Address is matched successfully (ADDR7F=1). Reading STS1 and then STS2 clears the
ADDR7F bit. In this case, the master enters transmit stage, and both DT register and internal shift
regiser are empty. The TDBE bit is set 1 by hardware.
5.
EV3: When the data is written to the DT register, it is directly moved to the shift register and the
SCL bus is released. The TDBE bit is still set 1 at this time.
6.
EV4: At this point, the DT register remains empty but the shift register is not. Writing to the DT
register clears the TDBE bit.
7.
The TDBE bit is set only after the second-to-last byte is sent.
8.
EV5: TDC=1 indicates that the byte transmission is complete. The master sends Stop condition
(STOPF=1). The TDBE bit and TDC bit is cleared by hardware.
9.
End of communication.
Master receiver
Data reception depends on I
2
C interrupt priority:
1.
Very high priority
When the second-to-last byte is being read, clear the ACKEN bit and set the GENSTOP bit in the
I2C_CTRL1 register to generate a Stop condition.
If only one byte is received, clear the ADDR7F flag and set the ACKEN and GENSTOP bit in the
I2C_CTRL1 register.
After the byte is received, the I2C_STS1_RDBF bit is set 1 by hardware, and it is cleared after
the software reads the I2C_DT register.