ARTERY AT32F413 Series, Reference Manual, Page: 333 / 369

AT32F413 Series Reference Manual
2022.06.27 Page 333 Rev 2.00
22.6.3 Control register 2 (ACC_CTRL2)
Bit Register Reset value Type Description
Bit 31: 14 Reserved 0x00000 resd
Forced to 0 by hardware
Bit 13: 8 HICKTRIM 0x00 ro
Internal high-speed auto clock trimming
This field is read only, but not written.
Internal high-speed clock is adjusted by ACC module,
which is added to the ACC_HICKCAL[7: 0] bit. These bits
allow the users to input a trimming value to adjust the
frequency of the HICKRC oscillator according to the
variations in voltage and temperature.
The default value is 32, which can trim the HICK to
8MHz±0.25. The trimming value is 20kHz (design value)
between two consecutive ACC_HICKTRIM steps.
Bit 7: 0 HICKCAL 0x00 ro
Internal high-speed auto clock calibration
This field is read only, but not written.
Internal high-speed clock is adjusted by ACC module.
These bits allow the users to input a trimming value to
adjust the frequency of the HICKPC oscillator according to
the variations in voltage and temperature.
The default value is 128, which can trim the HICK to
8MHz±0.25. The trimming value is 40kHz (design value)
between two consecutive ACC_HICKCAL steps.
22.6.4 Compare value 1 (ACC_C1)
Bit Register Reset value Type Description
Bit 31: 16 Reserved 0x0000 resd
Forced to 0 by hardware
Bit 15: 0 C1 0x1F2C rw
Compare 1
This value is the lower boundary for triggering calibration,
and its default value is 7980. When the number of clocks
sampled by ACC in 1ms period is less than or equal to C1,
auto calibration is triggered automatically.
When the actual sampling value (number of clocks in 1ms)
is greater than C1 but less than C3, auto calibration is not
enabled.
22.6.5 Compare value 2 (ACC_C2)
Bit Register Reset value Type Description
Bit 31: 16 Reserved 0x0000 resd
Forced to 0 by hardware
Bit 15: 0 C2 0x1F40 rw
Compare 2
This value defines the number of clocks sampled for 8MHz
(ideal frequency) clock in 1ms period , and its default value
is 8000 (theoretical value)
As a center point of cross-return strategy, this value is used
to calculate the calibration value closest to the theoretical
value. In theory, the actual frequency after calibration can
be trimmed to be within an accuracy of 0.5 steps from the
targe frequency (8MHz)
22.6.6 Compare value 3 (ACC_C3)
Bit Register Reset value Type Description
Bit 31: 16 Reserved 0x0000 resd Forced to 0 by hardware
Bit 15: 0 C3 0x1F54 rw
Compare 3
This value is the upper boundary for triggering calibration.
When the number of clock sampled by ACC in 1ms period
is greater than or equal to C3, auto calibration is triggered
automatically.
When the actual sampling value (number of clocks in 1ms
period) is greater than C1 but less than C3, auto calibration
is not enabled.