AT32F413
Series Reference Manual
2022.06.27
Page 192
Rev 2.00
Figure 14-22
Example of suspend mode
0
1
2
3
4
5
6
7
8
9
COUNTER
A
B
C
D
10
PR[15:0]
TMR_CLK
0
DIV[15:0]
32
101
STIS[2
：
0]
101
SMSEL[2
：
0]
CI1F1
TMR_EN
CNT_CLK
Slave mode: Trigger mode
The counter can start counting on the rising edge of a selected trigger input (TMR_EN=1)
Figure 14-23
Example of trigger mode
0
1
2
3
4
5
COUNTER
PR[15:0]
TMR_CLK
0
DIV[15:0]
32
101
STIS[2
：
0]
110
SMSEL[2
：
0]
CI1F1
TMR_EN
6
7
9
10
A
B
...
30
31
0
1
2
3
4
8
32
OVFIF
Master/slave timer interconnection
Both Master and slave timer can be configured in different master and slave modes respectively. The
combination of both them can be used for various purposes. Figure 14-24 provides an example of
interconnection between master timer and slave timer.
Figure 14-24
Master/slave timer connection
MMSEL
TRGOUT
Slave
mode
Select
STIS
SMSEL
CK_DIV
Prescaler
Input trigger
selection
Master Timer
Slave Timer
UEV
Counter
ISx
C1INC
C1IFP1
C2IFP2
EXT
TMREN
CxORAW
Master mode
selection
Using master timer to clock the slave timer:
Configure master timer output signal TRGOUT as an overflow event (PTOS[2: 0]=3’b010). The
master timer outputs a pulse signal at each counter overflow event, which is used as the
counting clock of the slave timer.
Configure the master timer counting period (TMRx_PR registers)