AT32F413
Series Reference Manual
2022.06.27
Page 43
Rev 2.00
The wakeup event can be generated by the following:
Enabling a peripheral interrupt (it is not enabled in the NVIC) and enabling the SEVONPEND bit.
When the MCU resumes, the peripheral interrupt pending bit and NVIC channel pending bit must
be cleared.
Configuring an internal EXINT line as an event mode to generate a wakeup event.
The wakeup time required by a WFE command is the shortest, since no time is wasted on interrupt
entry/exit.
Deepsleep Mode
Deepsleep mode is entered by setting the SLEEPDEEP bit in the Cortex
™
-M4F system control register
and clearing the LPSEL bit in the power control register before WFI or WFE instructions.
The LDO status is selected by setting the VRSEL bit in the power control register (PWC_CTRL). When
VRSEL=0, the LDO works in normal mode. When VRSEL=1, the LDO is set in low-power consumption
mode.
In Deepsleep mode, all clocks in 1.2 V domain are stopped, and both HICK and HEXT oscillators are
disabled. The LDO supplies power to the 1.2 V domain in normal mode or low-power mode. All I/O pins
keep the same state as in Run mode. SRAM and register contents are preserved.
1)
When the Sleep mode is entered by executing a WFI instruction, the interrupt generated on any
external interrupt line in Interrupt mode can wake up the system from Deepsleep mode.
2)
When the Sleep mode is entered by executing a WFE instruction, the interrupt generated on any
external interrupt line in Event mode can wake up the system from Deepsleep mode.
When the MCU exits the Deepsleep mode, the HICK RC oscillator is enabled and selected as a system
clock after stabilization.When the LDO operates in low-power mode, an additional wakeup delay is
incurred for the reason that the LDO must be stabilized before the system is waken from the Deepsleep
mode.
Standby Mode
Standby mode can achieve the lowest power consumption for the device. In this mode, the LDO is
disabled. The whole 1.2 V domain, PLL, HICK and HEXT oscillators are also powered off. SRAM and
register contents are lost. Only registers in the battery powered domain and standby circuitry remain
supplied.
The Standby mode is entered by the following procedures:
–
Set the SLEEPDEE bit in the Cortex
™
-M4F system control register
–
Set the LPSEL bit in the power control register (PWC_CTRL)
–
Clear the SWEF bit in the power control/status register (PWC_CTRLSTS)
–
Execute a WFI/WFE instruction
In Standby mode, all I/O pins remain in a high-impedance state except reset pins, TAMPER pins that
are set as anti-tamper or calibration output, and the wakeup pins enabled.
The MCU leaves the Standby mode when an external reset (NRST pin), an WDT reset, a rising edge on
the WKUP pin or the rising edge of an RTC alarm even occurs.
Debug mode
By default, the debug connection is lost if the MCU enters Deepsleep mode or Standby mode while
debugging. The reason is that the Cortex
™
-M4F core is no longer clocked. However, the software can
be debugged even in the low-power mode by setting some configuration bits in the DEBUG register
(DEBUG_CTRL).