manualshive.com logo in svg

ARTERY AT32F413 Series, Reference Manual, Page: 131 / 369

Share
Download
ARTERY AT32F413 Series Reference Manual Download Page 131

  AT32F413

 

Series  Reference  Manual

 

2022.06.27

 

Page 131 

 

Rev 2.00

 

stage at this time. 

7. 

EV3: RDBF=1. Reading the I2C_DT register clears the RDBF. 

8. 

End of communication. 

11.4.3  Utilize DMA for data transfer 

I

2

C data transfer can be done using DMA controller. An interrupt is generated by enabling the transfer 

complete interrupt bit. The DATAIEN bit in the I2C_CTRL2 register must be set 0 when using DMA for 
data transfer. The following sequence is for data transfer with DMA.

 

Transmission using DMA 

1. 

Set the peripheral address (DMA_CxPADDR=

 I2C_D

T address)

 

2. 

Set the memory address (DMA_CxMADDR=data memory address)

 

3. 

The transmission direction is set from memory to peripheral (DTD=1 in the DMA_CHCTRL 
register)

 

4. 

Configure the total number of bytes to be transferred in the DMA_CxDTCNT register

 

5. 

Configure  other  parameters  such  as  priority,  memory  data  width,  peripheral  data  width, 
interrupts, etc in the DMA_CHCTRL register

 

6. 

Enable the DMA channel by setting CHEN=1 in the DMA_CxCTRL register

 

7. 

Enable  I

2

C

 DMA request by setting DMAEN=1 in the 

I2C_CTRL2 register. Once the TDBE 

bit    in the 

I2C_STS1 register is set, the data is loaded from the programmed memory to the 

I2C_DT register through DMA

 

 

8. 

When  the  number  of  data  transfers,  programmed  in  the  DMA  controller,  is  reached 
(DMA_CxDTCNT=0), the data transfer is complete (An interrupt is generated if enabled).

 

9. 

Master transmitter: Once the TDC flag is set, the STOP condition is generated, indicating that 
transfer is complete. 

Slave transmitter: Once the ACKFAIL flag is set, clear the ACKFAIL flag, transfer is complete. 

 

Reception using DMA 

1. 

Set the peripheral address (DMA_CxPADDR =

 I2C_DT address

)

 

2. 

Set the memory address (DMA_CxMADDR = memory address)

 

3. 

The  transmission  directionis  set  from  peripheral  to  memory  (DTD=0  in  the  DMA_CHCTRL 
register)

 

4. 

Configure the total number of bytes to be transferred in the DMA_CxDTCNT register

 

5. 

Configure  other  parameters  such  as  priority,  memory  data  width,  peripheral  data  width, 
interrupts, etc in the DMA_CHCTRL register

 

6. 

Enable the DMA channel by setting CHEN=1 in the DMA_CxCTRL register

 

7. 

Enable 

I

2

C

 DMA request by setting DMAEN=1 in the 

I2C_CTRL2 register. Once the RDBE 

bit    in the 

I2C_STS1  register  is  set,  the  data  is  loaded  from  the 

I2C_DT  register

  to  the 

programmed memory

 through DMA 

8. 

When  the  number  of  data  transfers,  programmed  in  the  DMA  controller,  is  reached 
(DMA_CxDTCNT=0), the data transfer is complete (An interrupt is generated if enabled).

 

9. 

Master receiver: Clear the ACKFAIL flag, the STOP condition is generated, indicating that the 
transfer  is  complete  (when  the  number  of  bytes  to  be  transferred  is  greater  >=2  and 
DMAEND=1,  the  NACK  signal  is  generated  automatically  after  transfer  complete 
(DMA_CxDTCNT=0)) 

Slave receiver: Once the STOPF flag is set, clear the STOPF flag, and the transfer is complete.

 

Summary of Contents for AT32F413 Series

Page 1: ...t 0 5 s A D converters up to 16 channels Conversion range 0 V to 3 6 V Dual sample and hold capability Temparature sensor DMA 12 channel DMA controller Peripherals supported timers ADCs SDIOs I2 Ss SP...

Page 2: ...rmation 35 1 3 1 Flash memory size register 35 1 3 2 Device electronic signature 35 2 Memory resources 36 2 1 Internal memory address map 36 2 2 Flash memory 37 2 3 SRAM memory 38 2 4 Peripheral addre...

Page 3: ...pheral reset register CRM_APB1RST 55 4 3 6 APB peripheral clock enable register CRM_AHBEN 56 4 3 7 APB2 peripheral clock enable register CRM_AHB2EN 57 4 3 8 APB1 peripheral clock enable register CRM_A...

Page 4: ...n status register FLASH_EPPS 78 5 7 9 Flash unlock register3 FLASH_UNLOCK3 79 5 7 10 Flash select register FLASH_SELECT 79 5 7 11 Flash status register3 FLASH_STS3 79 5 7 12 Flash control register3 FL...

Page 5: ...A F 88 6 3 7 GPIO write protection register GPIOx_WPR x A F 88 7 Multiplexed function I Os IOMUX 89 7 1 Introduction 89 7 2 Function overview 89 7 2 1 IOMUX structure 89 7 2 2 Multiplexed input config...

Page 6: ...EXINT_INTEN 103 8 3 2 Event enable register EXINT_EVTEN 103 8 3 3 Polarity configuration register1 EXINT_ POLCFG1 103 8 3 4 Polarity configuration register2 EXINT_ POLCFG2 103 8 3 5 Software trigger r...

Page 7: ...10 2 3 Control register CRC_CTRL 119 10 2 4 Initialization register CRC_IDT 119 11 I2 C interface 120 11 1 I2C introduction 120 11 2 I2C main features 120 11 3 I2C function overview 120 11 4 I2C inte...

Page 8: ...12 6 1 Introduction 148 12 6 2 Configuration 148 12 7 Transmitter 148 12 7 1 Transmitter introduction 148 12 7 2 Transmitter configuration 149 12 8 Receiver 149 12 8 1 Receiver introduction 149 12 8...

Page 9: ...ode selector 169 13 3 3 Audio protocol selector 170 13 3 4 I2S_CLK controller 171 13 3 5 DMA transfer 174 13 3 6 Transmitter Receiver 174 13 3 7 I2S communication timings 175 13 3 8 Interrupts 176 13...

Page 10: ...4 6 Software event register TMRx_SWEVT 199 14 1 4 7 Channel mode register1 TMRx_CM1 200 14 1 4 8 Channel mode register2 TMRx_CM2 202 14 1 4 9 Channel control register TMRx_CCTRL 203 14 1 4 10 Counter...

Page 11: ...TMR9_C1DT 219 14 2 4 12 Channel 2 data register TMR9_C2DT 219 14 2 5 TMR10 and TMR11 registers 220 14 2 5 1 Control register1 TMRx_CTRL1 220 14 2 5 2 DMA interrupt enable register TMRx_IDEN 221 14 2...

Page 12: ...14 3 4 12 TMR1 and TMR8 period register TMRx_PR 248 14 3 4 13 TMR1 and TMR8 repetition period register TMRx_RPR 248 14 3 4 14 TMR1 and TMR8 channel 1 data register TMRx_C1DT 248 14 3 4 15 TMR1 and TM...

Page 13: ...control register high RTC_CTRLH 261 17 5 2 RTC control register low RTC_CTRLL 262 17 5 3 RTC divider register RTC_ DIVH RTC_DIVL 262 17 5 4 RTC divider counter register RTC_ DIVCNTH RTC_DIVCNTL 263 1...

Page 14: ...19 4 4 1 Data alignment 276 19 4 4 2 Data read 276 19 4 5 Voltage monitor 276 19 4 6 Status flag and interrupts 276 19 5 Master Slave mode 277 19 5 1 Data management 277 19 5 2 Regular simultaneous m...

Page 15: ...ission 299 20 6 6 Message reception 301 20 6 7 Error management 302 20 7 CAN registers 302 20 7 1 CAN control and status registers 303 20 7 1 1 CAN master control register CAN_MCTRL 303 20 7 1 2 CAN m...

Page 16: ...r CAN_ FiFBx i 0 13 x 1 2 318 21 Universal serial bus full seed device interface USBFS 319 21 1 USBFS introduction 319 21 2 USBFS clock and pin configuration 319 21 2 1 USB clock configuration 319 21...

Page 17: ...1 ACC_CTRL1 332 22 6 3 Control register 2 ACC_CTRL2 333 22 6 4 Compare value 1 ACC_C1 333 22 6 5 Compare value 2 ACC_C2 333 22 6 6 Compare value 3 ACC_C3 333 23 SDIO interface 334 23 1 SDIO introduct...

Page 18: ...7 23 4 8 SDIO data length register SDIO_DTLEN 357 23 4 9 SDIO data control register SDIO_DTCTRL 358 23 4 10 SDIO data counter register SDIO_DTCNTR 359 23 4 11 SDIO status register SDIO_STS 359 23 4 12...

Page 19: ...7 System data area programming process 73 Figure 6 1 GPIO basic structure 84 Figure 7 1 Basic structure of IOMUX basic structure 89 Figure 8 1 External interrupt Event controller block diagram 102 Fig...

Page 20: ...t with CK_INT divided by 1 183 Figure 14 3 Block diagram of external clock mode A 184 Figure 14 4 Counting in external clock mode A 184 Figure 14 5 Block diagram of external clock mode B 184 Figure 14...

Page 21: ...ivided by 1 226 Figure 14 46 Block diagram of external clock mode A 226 Figure 14 47 Counting in external clock mode A 226 Figure 14 48 Block diagram of external clock mode B 226 Figure 14 49 Counting...

Page 22: ...g 291 Figure 20 2 Transmit interrupt generation 293 Figure 20 3 Transmit interrupt generation 294 Figure 20 4 Receive interrupt 0 generation 294 Figure 20 5 Receive interrupt 1 generation 294 Figure 2...

Page 23: ...ort map 91 Table 7 5 IOMUX register map and reset value 92 Table 8 1 External interrupt Event controller register map and reset value 103 Table 9 1 DMA error event 108 Table 9 2 DMA interrupt requests...

Page 24: ...and reset values 302 Table 21 1 Buffer size configuration table 320 Table 21 2 USBFS register map and reset values 322 Table 22 1 ACC interrupt requests 328 Table 22 2 ACC register map and reset value...

Page 25: ...AT32F413 Series Reference Manual 2022 06 27 Page 25 Rev 2 00 Table 24 1 Trace function enable 364 Table 24 2 Trace function mode 365 Table 24 3 DEBUG register address and reset value 365...

Page 26: ...er MAC dual 16 bit MAC instruction optimized 8 bit 16 bit SIMD operation and saturation operation instruction and single precision IEEE 754 float point unit FPU as shown in Figure 1 1 Figure 1 1 AT32F...

Page 27: ...pplications that require quicker response to interruption Cortex M4F processor is based on ARMv7 M architecture supporting both Thumb instruction set and DSP instruction set Figure 1 2 shows the inter...

Page 28: ...ias region image B 0 bitband alias region total 32M bytes 0x2000_0000 0x2000_0001 0x2000_0002 0x2000_0003 0x2200_001C 1 2 3 4 5 6 7 0x2200_0018 0x2200_0014 0x2200_0010 0x2200_000C 0x2200_0008 0x2200_0...

Page 29: ..._0004 0 0x2000_0000 2 0x2200_0008 0 0x2000_0000 31 0x2200_007C 0 0x2000_0004 0 0x2200_0080 0 0x2000_0004 1 0x2200_0084 0 0x2000_0004 2 0x2200_0088 0 0x200F_FFFC 31 0x23FF_FFFC 0 Table 1 2 shows the ma...

Page 30: ...lt 0x0000_000C 0 Configur able MemoryManage Memory management 0x0000_0010 1 Configur able BusFault Pre fetch fault memory access fault 0x0000_0014 2 Configur able UsageFault Undefined instruction or i...

Page 31: ...FS_H_CAN1_TX USBFS high priority or CAN1 TX interrupt0x0000_008C 20 27 Configur able USBFS_L_CAN1_RX0 USBFS low priority or CAN1 RX0 interrupt 0x0000_0090 21 28 Configur able CAN1_RX1 CAN1 RX1 interru...

Page 32: ...rupt 0x0000_00F0 45 52 Configur able TMR8_TRG_HALL TMR8 trigger and HALL interrupt 0x0000_00F4 46 53 Configur able TMR8_CH TMR8 channel interrupt 0x0000_00F8 47 54 Reserved 0x0000_00FC 48 55 Reserved...

Page 33: ...will be reloaded with the initial value automatically when it is decremented to zero It can generate periodic interrupts so it is often used as multi task scheduling counter for embedded operating sy...

Page 34: ...Exception Vectors Boot Code Other Memory Code Stack Memory Stack grows downward Initial SP Value 0x2000_8000 0x0000_0000 0x0000_0004 0x0000_0100 0x2000_7C00 0x2000_7FFC 0x2000_7FF8 0x2000_8000 In the...

Page 35: ...abbreviations for registers Register abbr Base address Reset value F_SIZE 0x1FFF F7E0 0xXXXX UID 31 0 0x1FFF F7E8 0xXXXX XXXX UID 63 32 0x1FFF F7EC 0xXXXX XXXX UID 95 64 0x1FFF F7F0 0xXXXX XXXX 1 3 1...

Page 36: ...0x0803_FFFF Reserved External SPI Flash memory 0x0804_0000 0x083F_FFFF 0x0840_0000 0x1FFF_B000 Boot Memory User System Data 0x1FFF_F800 0x1FFF_EFFF 0x1FFF_F82F 0x1FFF_FFFF Reserved Aliased to Flash o...

Page 37: ...ternal memory 16MB Page 0 0x0840 0000 0x0840 0FFF Page 1 0x0840 1000 0x0840 1FFF Page 2 0x0840 2000 0x0840 2FFF Page 4095 0x093F F000 0x093F FFFF Information block 16 KB boot loader 0x1FFF B000 0x1FFF...

Page 38: ...ecial mode that supports dynamic switch between 16 KB and 64 KB of SRAM This is done by setting the EOPB0 bit In 64 KB mode Flash memory size zero wait sate is limited to 64 KB while in 16 KB mode the...

Page 39: ...4000 73FF Power control PWC 0x4000 6C00 0x4000 6FFF Battery powered domain register BPR 0x4000 6800 0x4000 6BFF CAN2 0x4000 6400 0x4000 67FF CAN1 0x4000 6000 0x4000 63FF USBFS 512 bytes buffer 1 0x400...

Page 40: ...domain and battery powered domain The VDD VDDA domain is supplied directly by external power the 1 2 V domain is powered by the embedded LDO in the VDD VDDA domain and the battery powered domain is su...

Page 41: ...gure 3 2 Power on reset Low voltage reset waveform Reset VDD VLVR VPOR Temporization tRESTTEMPO VPOR VLVR hysteresis 3 4 Power voltage monitor PVM The PVM is used to monitor the power supply variation...

Page 42: ...disconnected from VBAT because of the VDD being at its rising phrase or due to VDD low voltage reset If the power switch has not been switched to the VDD when the VDD is powered on quickly it is reco...

Page 43: ...generated on any external interrupt line in Event mode can wake up the system from Deepsleep mode When the MCU exits the Deepsleep mode the HICK RC oscillator is enabled and selected as a system clock...

Page 44: ...Bit 7 5 PVMSEL 0x0 rw Power voltage monitoring boundary select 000 Unused not configurable 001 2 3 V 010 2 4 V 011 2 5 V 100 2 6 V 101 2 7 V 110 2 8 V 111 2 9 V Bit 4 PVMEN 0x0 rw Power voltage monito...

Page 45: ...Power voltage monitoring output flag 0 Power voltage is higher than the threshold 1 Power voltage is lower than the threshold Note The power voltage monitor is stopped in Standby mode Bit 1 SEF 0x0 r...

Page 46: ...and APB2 are up to 100 MHz 4 1 1 Clock sources High speed external oscillator HEXT The HEXT includes two clock sources HEXT crystal ceramic resonator and HEXT bypass clock The HEXT crystal ceramic res...

Page 47: ...target clock source becomes stable When the HICK oscillator is used directly or indirectly through the PLL as the system clock it cannot be stopped 4 1 3 Peripheral clock Most peripherals use HCLK PCL...

Page 48: ...n the AHB bus resumes 4 1 6 Internal clock output The microcontroller allows the internal clock signal to be output to an external CLKOUT pin That is ADC CLK USB48M SCLK LICK LEXT HICK HEXT PLL 2 and...

Page 49: ...on if both supplies have been powered off Software reset affects only the battery powered domain 4 3 CRM registers These peripheral registers have to be accessed by bytes 8 bits half words 16 bits or...

Page 50: ...6 HEXTEN 0x0 rw High speed external crystal enable This bit is set and cleared by software It can also be cleared by hardware when entering Standby or Deepsleep mode When the HEXT clock is used as the...

Page 51: ...clock 000 PLL clock divided by 1 5 to be USB clock 001 PLL clock is directly to be USB clock 010 PLL clock divided by 2 5 to be USB clock 011 PLL clock divided by 2 to be USB clock 100 PLL clock divid...

Page 52: ...at the APB2 clock frequency is less than 100 MHz Bit 10 8 APB1DIV 0x0 rw APB1 division HCLK frequency division is used as APB1 clock 0xx HCLK is not divided 100 HCLK is divided by 2 101 HCLK is divide...

Page 53: ...No effect 1 Clear Bit 17 LEXTSTBLFC 0x0 wo LEXT stable flag clear Writing 1 by software to clear LEXTSTBLF 0 No effect 1 Clear Bit 16 LICKSTBLFC 0x0 wo LICK stable flag clear Writing 1 by software to...

Page 54: ...ccessible no wait state word half word and byte Bit Name Reset value Type Description Bit 31 23 Reserved 0x000 resd Kept at its default value Bit 22 ACCRST 0x0 rw ACC reset 0 No effect 1 Reset Bit 21...

Page 55: ...Reset 4 3 5 APB1 peripheral reset register CRM_APB1RST Accessible no wait state word half word and byte Bit Name Reset value Type Description Bit 31 CAN2RST 0x0 rw CAN2 reset 0 No effect 1 Reset Bit 3...

Page 56: ...eset Bit 0 TMR2RST 0x0 rw TMR2 reset 0 No effect 1 Reset 4 3 6 APB peripheral clock enable register CRM_AHBEN Accessible no wait state word half word and byte Note When a peripheral clock is disabled...

Page 57: ...sd Kept at its default value Bit 22 ACCEN 0x0 rw ACC clock enable 0 Disabled 1 Enabled Bit 21 TMR11EN 0x0 rw TMR11 clock enable 0 Disabled 1 Enabled Bit 20 TMR10EN 0x0 rw TMR10 clock enable 0 Disabled...

Page 58: ...il the completion of the peripheral access on APB2 Note When a peripheral clock is disabled reading this register by software always returns 0x0 Bit Name Reset value Type Description Bit 31 CAN2EN 0x0...

Page 59: ..._BPDC Access 0 to 3 wait states Wait states are inserted in the case of consecutive accesses to this register Note LEXTEN LEXTBYPS RTCSEL and RTCEN bits of the battery powered domain control register...

Page 60: ...Low power reset occurs Bit 30 WWDTRSTF 0x0 ro Window watchdogtimer reset flag Sety by hardware Cleared by writing to the RSTFC bit 0 No window watchdogtimer reset occurs 1 Window watchdogtimer reset o...

Page 61: ...ct HICK or HICK 6 If the HICK 6 is selected the clock frequency is 8 MHz Otherwise the clock frequency is 48 MHz 0 HICK 6 1 HICK Note In any case HICK always input 4 MHz to PLL Bit 24 USBBUFS 0x0 rw U...

Page 62: ...s switched from others to the PLL or when the AHB prescaler is changed from large to small system frequency is from small to large it is recommended to enable the auto step by step system clock switch...

Page 63: ...External memory 16MB Page 0 0x0840 0000 0x0840 0FFF Page 1 0x0840 1000 0x0840 1FFF Page 2 0x0840 2000 0x0840 2FFF Page 4095 0x093F F000 0x093F FFFF Information block 16 KB boot loader 0x1FFF B000 0x1F...

Page 64: ...FFF F82F External memory External Flash memory controls the external SPI Flash through SPIM transmission interface It supports ciphertext protection User can decide whether or not to encrypte the data...

Page 65: ...x31 Write Status Register 1 0x01 Write Status Register 2 0x31 Note 1 If it is mandatory to set the QE to 1 in the Status Register before executing 0x32 and 0xEB then 0x1 Flash is selected by seting th...

Page 66: ...on is disabled 15 8 nEPP0 7 0 Inverse code of EPP0 7 0 23 16 EPP1 7 0 Flash erase write protection byte 1 stored in the FLASH_EPPS 15 8 For 256 K Flash memory this field is used to protect page 16 pag...

Page 67: ...of EXT_FLASH_KEY4 7 0 23 16 EXT_FLASH_KEY5 7 0 External memory ciphertext encryption key byte 5 31 24 nEXT_FLASH_KEY5 7 0 Inverse code of EXT_FLASH_KEY5 7 0 0x1FFF_F82C 7 0 EXT_FLASH_KEY6 7 0 Externa...

Page 68: ...t in FLASH_STSx No Yes End Mass erase Mass erase function can erase the whole Flash memory The following process is recommended Check the OBF bit in the FLASH_STS register to confirm that there is no...

Page 69: ...Page 69 Rev 2 00 Figure 5 4 Flash memory mass erase process Start No Check the OBF bit in FLASH_STSx OBF 0 Yes Set BANKERS 1 and ERSTR 1 in FLASH_CTRLx OBF 0 Check the OBF bit in FLASH_STSx Read EPPE...

Page 70: ...the FLASH_STS register becomes 0 read the EPPERR PRGMERR and ODF bit to verify the programming result Note 1 When the address to be written is not erased in advance the programming operation is not ex...

Page 71: ...the FLASH_USD_UNLOCK register the USDULKS bit in the FLASH_CTRL register will be automatically set by hardware indicating that the user system data area can be programmed write erase Note Writing an i...

Page 72: ...owing process is recommended Check the OBF bit in the FLASH_STS register to confirm that there is no other programming operation in progress Set the USDPRGM bit in the FLASH_CTRL register so that the...

Page 73: ...L Write word half word 32bits 16 bits data No Yes Start Check the OBF bit in FLASH_STS No Check the OBF bit in FLASH_STS OBF 0 Yes Read PRGMERR bit and ODF bit in FLASH_STS End 5 4 4 Read operation Us...

Page 74: ...ader Boot from main Flash memory Read Write Erase Read Write Erase Main Flash memory Not allowed Not allowed 1 2 Accessible External memory Not allowed Not allowed 2 Accessible User system data area N...

Page 75: ...Program codes to be protected by the security library should not be placed on the first page of Flash memory Only I Code bus is allowed to read instruction security library Only D Code bus is allowed...

Page 76: ...ue Register Offset Reset value FLASH_PSR 0x00 0x0000 0030 FLASH_UNLOCK 0x04 0xXXXX XXXX FLASH_USD_UNLOCK 0x08 0xXXXX XXXX FLASH_STS 0x0C 0x0000 0000 FLASH_CTRL 0x10 0x0000 0080 FLASH_ADDR 0x14 0x0000...

Page 77: ...ng 1 Bit 3 Reserved 0x0 resd Kept at its default value Bit 2 PRGMERR 0x0 rw Programming error When the programming addess is not 0xFFFF this bit is set by hardware It is cleared by writing 1 Bit 1 Res...

Page 78: ...FA 0x0000 0000 wo Flash address Select the address of the pages to be erased in page erase operation 5 7 7 User system data register FLASH_USD Bit Register Reset value Type Description Bit 31 26 Reser...

Page 79: ...g the erase program protected Flash memory address It is cleared by writing 1 Bit 3 Reserved 0x0 resd Kept at its default value Bit 2 PRGMERR 0x0 rw Programming error When the programming addess is no...

Page 80: ...nal memory 5 7 14 Flash decrption address register FLASH_DA For external memory only Bit Register Reset value Type Description Bit 31 0 FDA 0x0000 0000 wo Flash decryption address Set the encryption r...

Page 81: ...The write status of this register is reflected in the bit 0 and bit 1 in the SLIB_MISC_STS register 5 7 18 Security library additional status register SLIB_MISC_STS For Flash security library only Bi...

Page 82: ...11 SLIB_DSS_SET 0x000 wo Security library data start page setting These bits are used to set the security library start page 0 Invalid page Setting it will cause security library to fail to start 1 P...

Page 83: ...ly after the hardware enables CRC Bit 13 7 CRC_SN 0x000 wo CRC calibration page numbler Set the number of the CRC calibarion in terms of pages Bit 6 0 CRC_SS 0x000 wo CRC calibration start page Set th...

Page 84: ...rain output multiplexed push pull open drain output Each pin s output drive capability and output signal slope is configureable by software Each pin can be configured as external interrupt input Each...

Page 85: ...HDRV IOMC 1 IOMC 0 ODT register Analog input output 00 000 Unused When I O port is configured as analog input Schmitt trigger input is disabled Digital input output is disabled Without any pull up pul...

Page 86: ...26 Bit 23 22 Bit 19 18 Bit 15 14 Bit 11 10 Bit 7 6 Bit 3 2 IOFCy 0x1 rw GPIOx function configuration y 0 7 In input mode IOMCy 1 0 00 00 Analog mode 01 Floating input after reset 10 Pull up pull down...

Page 87: ...e reset state 01 Output mode large sourcing sinking strength 10 Output mode normal sourcing sinking strength 11 Output mode normal sourcing sinking strength Note Some port registers have different res...

Page 88: ...R x A F Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 0 IOCB 0x0000 wo GPIOx clear bit The corresponding ODT register bits are cleared by wr...

Page 89: ...gured as input modes floating pull up and pull down input To enable multiplexed function output the port is configured as multiplexed function output mode push pull or open drain by setting GPIOx_CFGL...

Page 90: ...er of the desired peripheral IOMUX functions in different packages Pin mapping is achieved by setting the IOMUX_REMAP and IOMUX_REMAPx registers x 2 3 8 Table 7 2 IOMUX output configuration Mode IOFC...

Page 91: ...by other peripherals To utilize more pins during this period the above mentioned remap configuration can be changed by setting the SWJTAG_MUX 2 0 bit in the IOMUX_REMAP register and SWJTAG_GMUX 2 0 bi...

Page 92: ...OMUX_REMAP8 0x34 0x0000 0000 Note IOMUX clock must be enabled before read write access to IOMUX_EVTOUT IOMUX_REMAPx and IOMUX_EXINTx 7 3 1 Event output control register IOMUX_EVTOUT Bit Register Reset...

Page 93: ...C2_ETP_MUX 0x0 rw ADC2 external trigger preempted conversion mutiplexing Select external trigger input for ADC2 preempted conversion 0 ADC2 external trigger preempted conversion is connected to EXINT1...

Page 94: ...PB10 and CH4 PB11 Bit 7 6 TMR1_MUX 0x0 rw TMR1 IO multiplexing Select IO multiplexing for TMR1 00 EXT PA12 CH1 PA8 CH2 PA9 CH3 PA10 CH4 PA11 BRK PB12 CH1C PB13 CH2C PB14 CH3C PB15 01 EXT PA12 CH1 PA8...

Page 95: ...erved Bit 11 8 EXINT2 0x0000 rw EXINT2 input source configuration Select the input source for EXINT2 external interrupt 0000 GPIOA pin2 0001 GPIOB pin2 0010 GPIOC pin2 0011 GPIOD pin2 0100 GPIOF pin2...

Page 96: ...configuration Select the input source for EXINT5 external interrupt 0000 GPIOA pin5 0001 GPIOB pin5 0010 GPIOC pin5 0011 GPIOD pin5 0100 GPIOF pin5 Others Reserved Bit 3 0 EXINT4 0x0000 rw EXINT4 inp...

Page 97: ...pe Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 12 EXINT15 0x0000 rw EXINT15 input source configuration Select the input source for EXINT15 external interrupt 0000 GPIOA...

Page 98: ...2 PB15 7 3 9 IOMUX remap register4 IOMUX_REMAP4 Bit Register Reset value Type Description Bit 31 20 Reserved 0x000 resd Kept at its default value Bit 19 TMR5CH4_GMUX 0x0 rw TMR5 channel4 general multi...

Page 99: ...0 CS PB12 SCK PB13 MISO PB14 MOSI PB15 MCK PB0 0001 CS PA15 SCK PB3 MISO PB4 MOSI PB5 MCK PC7 Others Unused Bit 19 16 SPI1_GMUX 0x0 rw SPI1 IO general multiplexed function Select IO multiplexing for S...

Page 100: ...tiplexing for CAN2 0000 RX PB12 TX PB13 0001 RX PB5 TX PB6 Others Unused Bit 3 0 CAN1_GMUX 0x0 rw CAN1 IO general multiplexing Select IO multiplexing for CAN1 00 RX PA11 TX PA12 10 RX PB8 TX PB9 Other...

Page 101: ...nnel 4 Bit 7 6 Reserved 0x0 resd Keep at its default value Bit 5 ADC1_ETO_GMUX 0x0 rw ADC1 external trigger regular conversion general multiplexing Select the input source for ADC1 external trigger re...

Page 102: ...GPIO external interrupt sources but also internal sources such as PVM output RTC alarm events and USB wakeup events through edge detection mechanism where GPIO interrupt sources can be selected with...

Page 103: ...errupt enable or disable on line x 0 Interrupt request is disabled 1 Interrupt request is enabled 8 3 2 Event enable register EXINT_EVTEN Bit Register Reset value Type Description Bit 31 19 Reserved 0...

Page 104: ...ically to generate an interrupt If the corresponding bit in the EXINT_EVTEN register is 1 the software writes to this bit The hardward generates an event on the corresponding interrupt line automatica...

Page 105: ...Only support AHB OKAY and ERROR responses HBUSREQ and HGRANT of AHB master interface are not supported Support 7 channels Peripheral to memory memory to peripheral and memory to memory transfers Suppo...

Page 106: ...address plus transfer width PWIDTH MWIDTH Circular mode LM In circular mode the contents in the DMA_CxDTCNT register is automatically reloaded with the initially programmed value after the completion...

Page 107: ...IDTH and MWIDTH bits in the DMA_CxCTRL register When PWIDTH is not equal to MWIDTH it can be aligned according to the settings of PWIDTH MWIDTH Figure 9 3 PWIDTH byte MWIDTH half word B3 B2 B1 B0 Half...

Page 108: ...DTERRF DTERRFC DTERRIEN Note DMA 2 channel 4 channel 5 channel 6 channel 7 interrupts are mapped onto the same interrupt vector 9 3 7 Fixed DMA request mapping Several peripheral requests are mapped t...

Page 109: ...67 TMR2_CH4 99 reserved 4 reserved 36 reserved 68 reserved 100 reserved 5 reserved 37 reserved 69 TMR3_TRIG 101 reserved 6 reserved 38 reserved 70 reserved 102 reserved 7 reserved 39 reserved 71 TMR3_...

Page 110: ...ord 16 bits or word 32 bits Table 9 6 DMA register map and reset value Register Offset Reset value DMA_STS 0x00 0x0000 0000 DMA_CLR 0x04 0x0000 0000 DMA_C1CCTRL 0x08 0x0000 0000 DMA_C1DTCNT 0x0C 0x000...

Page 111: ...red 1 Transfer complete event occurred Bit 24 GF7 0x0 ro Channel global event flag 0 No transfer error half transfer or transfer complete event occurred 1 Transfer error half transfer or transfer comp...

Page 112: ...red Bit 9 FDTF3 0x0 ro Channel 3 transfer complete event flag 0 No transfer complete event occurred 1 Transfer complete event occurred Bit 8 GF3 0x0 ro Channel 3 global event flag 0 No transfer error...

Page 113: ...clear 0 No effect 1 Clear the DTERRF6 flag in the DMA_STS register Bit 22 HDTFC6 0x0 rw1c Channel 6 half transfer flag clear 0 No effect 1 Clear the HDTF6 flag in the DMA_STS register Bit 21 FDTFC6 0x...

Page 114: ...DMA_STS register Bit 7 DTERRFC2 0x0 rw1c Channel 2 data transfer error flag clear 0 No effect 1 Clear the DTERRF2 flag in the DMA_STS register Bit 6 HDTFC2 0x0 rw1c Channel 2 half transfer flag clear...

Page 115: ...ts 10 32 bits 11 Reserved Bit 9 8 PWIDTH 0x0 rw Peripheral data bit width 00 8 bits 01 16 bits 10 32 bits 1 Reserved Bit 7 MINCM 0x0 rw Memory address increment mode 0 Disabled 1 Enabled Bit 6 PINCM 0...

Page 116: ...can only be written when the CHEN bit in the corresponding channel is set 0 9 4 6 DMA channelx memory address register DMA_CxMADDR x 1 7 Accessible no wait state byte half word and word Bit Register...

Page 117: ...able 0 DMA fixed request mapping mode 1 DMA flexible request mapping mode Bit 23 16 CH7_SRC 0x00 rw CH7 source select When DMA_FLEX_EN 1 CH7_SRC selects channel 7 source please refer to 9 3 8 Flexible...

Page 118: ...format toggle Perform write read operation through CRC_DT register Set an initialization value with the CRC_IDT register The value is loaded with CRC_DT register after each CRC reset 10 2CRC registers...

Page 119: ...sed to control how to reverse input data 00 No effect 01 Byte reverse 10 Half word reverse 11 Word reverse Bit 4 1 Reserved 0x0 resd Kept at its default value Bit 0 RST 0x0 rw Reset CRC calculation un...

Page 120: ...rt DMA transfer Support partial SMBus2 protocol PEC generation and verification SMBus reminder function ARP address resolution protocol Timeout mechanism PMBus 11 3I2C function overview I2C bus consis...

Page 121: ...ode and slave mode Switching from master mode to slave mode vice versa is supported as well By default the interface operates in slave mode When GENSTART 1 is set Start condition is activated the I2 C...

Page 122: ...ng data 5 Clock stretching capability Clock stretching is enabled by setting the STRETCH bit in the I2C_CTRL1 register Once enabled when the slave cannot process data in a timely manner on certain con...

Page 123: ...ta2 A DataN NA P EV2 EV3 EV4 EV3 EV3 SCL Stretch 7 bit address 10 bit address R W 0 R W 1 R W 7 bit address mode 1 Wait for the master to send addresses 2 EV1 Address is matched ADDR7F 1 and then the...

Page 124: ...ss A SCL Stretch Data1 A Data2 A DataN A P EV2 EV3 EV1 7 bit address 10 bit address EV2 EV2 EV2 EV2 0 R W 0 R W 7 bit address mode 1 Wait for the master to send an address 2 EV1 Address is matched ADD...

Page 125: ...o address 9 8 and then slave address 7 0 the master enters transmitter mode Receiver First send slave address head 0b11110xx0 where xx refers to address 9 8 and then address 7 0 followed by the addres...

Page 126: ...6 10 bit address head sequence is sent Reading STS1 and writing to DT register clears the ADDRHF bit 4 EV2 Address is matched successfully ADDR7F 1 Reading STS1 and then STS2 clears the ADDR7F bit In...

Page 127: ...en STS2 clears the ADDR7F bit In this case the master enters receive stage 4 EV3 The RDBF bit is set 1 after a byte is received Reading the I2C_DT register clears the RDBF 5 EV4 Once the second to las...

Page 128: ...V3 EV4 DataN 2 A DataN 1 A SCL Stretch EV3 EV3 EV3 EV3 7 bit address R W 0 R W 1 R W SCL Stretch EV1 SCL Stretch EV1 EV2 SCL Stretch EV1 SCL Stretch 7 bit address mode 1 Generate a Start condition GEN...

Page 129: ...the event EV4 I2C_STS1_ADDR7F 1 reading STS1 and then STS2 will clear the event EV5 I2C_STS1_ADDRHF 1 reading STS1 and write I2C_DT register will clear the event EV2 EV3 RDBF Address Head S A SCL Stre...

Page 130: ...l clear the event EV5 I2C_STS1_ADDRHF 1 reading STS1 and write I2C_DT register will clear the event EV2 EV3 RDBF Address Head S A SCL Stretch Address A EV4 EV5 10 bit address Address Head RS SCL Stret...

Page 131: ...ansfer is complete An interrupt is generated if enabled 9 Master transmitter Once the TDC flag is set the STOP condition is generated indicating that transfer is complete Slave transmitter Once the AC...

Page 132: ...cation of these protocols SMBus address resolution protocol ARP SMBus address conflicts can be resolved by dynamically assigning a new uique address to each device Refer to SMBus 2 0 protocol for more...

Page 133: ...st transmitted byte DMA mode The PEC is transferred automatically after the last transmitted byte For example if the number of data to be transferred is 8 then DMA_TCNTx 8 PEC reception Common mode Se...

Page 134: ...e 1 I2 C peripheral is at reset state Note This bit can be used only when the BUSYF bit is 1 and no Stop condition is detected on the bus Bit 14 Reserved 0x0 resd Kept at its default value Bit 13 SMBA...

Page 135: ...0 rw General call address enable 0 Enabled 1 Disabled Bit 5 PECEN 0x0 rw PEC calculation enable 0 Disabled 1 Enabled Bit 4 ARPEN 0x0 rw SMBus address resolution protocol enable 0 Disabled 1 Enabled SM...

Page 136: ...mode ADDR7F 1 Master slave mode ADDRHF 1 Master mode STOPF 1 Slave mode TDC 1 but no TDBE or RDBF event If DATAIEN 1 the TDBE event is 1 If DATAIEN 1 the RDBF event is 1 Bit 8 ERRIEN 0x0 rw Error inte...

Page 137: ...copied into the DT register RDNE 1 A continuous data transfer flow can be maintained if the DT register is read before the next word is received RDNE 1 Note If an ARLOST event occurs on ACK pulse the...

Page 138: ...he data at this point 1 The data has been moved from the DT register to the shift register The data register is empty now This flag is set when the DT register is empty and cleared when writing to the...

Page 139: ...ondition generation complete flag 0 No Start condition is generated 1 Start condition is generated Cleared by write access to the DT register after the software reads the STS1 register 11 5 7 Status r...

Page 140: ...mode up to 100 kHz 1 Fast mode up to 400 kHz In fast mode an accurate 400kHz clock is generated when the I2 C clock frequency is an integer multiple of 10MHz Bit 14 DUTYMODE 0x0 rw Fast mode duty cyc...

Page 141: ...0 RISETIME 0x02 rw I2C bus rise time Time RISETIME x TI2C_CLK In standard mode I2C protocol stand is 1000ns and the formula as follows RISETIME FI2C_CLK 1 For example when I2C clock is 48MHz RISETIME...

Page 142: ...rd protcoal defined in ISO7816 3 standard and CTS RTS Clear To Send Request To Send hardware flow operation It also allows mutli processor communication and supports silent mode waken up by idle frame...

Page 143: ...e frame format Programmable data word length 8 bits or 9 bits Programmable stop bits support 1 or 2 stop bits Programmable parity control transmitter with parity bit transmission capability and receiv...

Page 144: ...configuration 12 3 2 Configuration procedure Selection of operation mode is done by following the configuration process listed below In addition such configuration method along with that of receiver a...

Page 145: ...ue 6 Synchronous mode By setting the CLKEN bit to 1 synchronous mode and clock pin output are enabled Select CK pin high or low in idle state by setting the CLKPOL bit 1 or 0 Whether to sample data on...

Page 146: ...op bits Set the PEN bit will enable parity control PSEL 1 indicates Odd parity while PSEL 0 for Even parity Once the parity control is enabled the MSB of the data bit will be replaced with parity bit...

Page 147: ...l register 5 Configure the channel priority of DMA transfer in the DMA control register 6 Configure DMA interrupt generation after half or full transfer in the DMA control register 7 Enable DMA transf...

Page 148: ...z fPCLK 72MHz No Kbps Actual Value programmed in the baud register Error Actual Value programmed in the baud register Error 1 2 4 2 4 15000 0 2 4 30000 0 2 9 6 9 6 3750 0 9 6 7500 0 3 19 2 19 2 1875 0...

Page 149: ...Wait unitl the TDBE bit is set the data to be transferred will be loaded into the USART_DT register This operatin will clear the TDBE bit Repeat this step in non DMA mode 10 After the last data expec...

Page 150: ...generated when the RDBFIEN is set The erro flag is set when a framing error noise error or overrun error is detected during reception In DMA mode the RDBF bit is set after every byte is received and...

Page 151: ...111 110 101 011 Any value 1 Invalid Any value 111 110 101 011 1 Invalid Note If the sampling values on the 3rd 5th 7th 8th 9th and 10th bits do not match the above mentioned requirements the USART re...

Page 152: ...flag CTSCF CTSCFIEN Transmit data complete TDC TDCIEN Receive data buffer full RDBF RDBFIEN Receiver overflow error ROERR Idle flag IDLEF IDLEIEN Parity error PERR PERRIEN Break frame flag BFF BFIEN N...

Page 153: ...his bit is set by hardware when the transmit data buffer is empty It is cleared by a USART_DT register write operation 0 Data is not transferred to the shift register 1 Data is transferred to the shif...

Page 154: ...RT_STS register followed by a USART_DT read operation 0 No parity error occurs 1 Parity error occurs 12 11 2Data register USART_DT Bit Register Reset value Type Description Bit 31 9 Reserved 0x000000...

Page 155: ...errupt is enabled Bit 5 RDBFIEN 0x0 rw RDBF interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled Bit 4 IDLEIEN 0x0 rw IDLE interrupt enable 0 Interrupt is disabled 1 Interrupt is enabled Bi...

Page 156: ...high Bit 9 CLKPHA 0x0 rw Clock phase This bit is used to select the phase of the clock output on the clock pin in synchronous mode or Smartcard mode 0 Data capture is done on the first clock edge 1 Da...

Page 157: ...rtcard mode enable 0 Smartcard mode is disabled 1 Smartcard mode is enabled Bit 4 SCNACKEN 0x0 rw Smartcard NACK enable This bit is used to send NACK when parity error occurs 0 NACK is disabled when p...

Page 158: ...smartcard mode Bit 7 0 ISDIV 0x00 rw IrDA smartcard division In IrDA mode 8 bit 7 0 is valid It is valid in common mode and must be set to 00000001 In low power mode it divides the peripheral clock t...

Page 159: ...controller SPI_STS BF ROE RR MME RR CCE RR TUER R ACS TDBE RDBF Communication controller CS controller SWCSEN SWCSIL SLBEN SLBTD ORA MDIV 3 0 CLKPOL CLKPHA MSTEN Transmitter logic Transmission CRC un...

Page 160: ...idirectional full duplex mode when the SLBEN bit and the ORA bit is both 0 In this case the SPI supports data transmission and reception at the same time IO connection is as follows Figure 13 2 SPI tw...

Page 161: ...SI pin is released The SLBTD bit is used by software to configure transfer direction When the SLBTD bit is set the SPI can be used only for data transmission when the SLBTD bit is 0 the SPI can be use...

Page 162: ...RR bit is set the SPIEN and MSTEN bits cannot be set by software The MMERR bit is cleared by read or write access to the SPI_STS register followed by write operation to the SPI_CTRL1 register In slave...

Page 163: ...tware receives the last data when the second to last data is received 13 2 6 DMA transfer The SPI supports write and read operations with DMA Refer to the following configuration procedure Special att...

Page 164: ...to write the data to be transmitted only when the TDBE is set After the transmitter is configured and the SPI is enabled the SPI is ready for data transmission Before going forward it is necessary for...

Page 165: ...pt RDBEIE 1 through the RDBE bit Configure frame format select MSB LSB mmode with the LTF bit and select 8 16 bit data with the FBN bit Enable SPI by setting the SPIEN 13 2 9 Motorola mode This sectio...

Page 166: ...transmit MOSI 0xaa 0xcc 0xaa Figure 13 8 Slave full duplex communications SCK BF flag CS MOSI 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 TDBE flag Drive Transmit buffer empty and software can wr...

Page 167: ...L 0 CLKPHA 0 SCK idle output low use the first edge for sampling FBN 0 8 bit frame Master receive 0xaa 0xcc 0xaa Figure 13 11 Master half duplex receive SCK BF flag CS MOSI 1 0 1 1 1 1 1 1 1 0 0 0 0 1...

Page 168: ...ave reception transmission supporting four kinds of audio protocols including Philips standard MSB aligned standard LSB aligned standard and PCM standard respectively The DMA transfer is also supporte...

Page 169: ...ice transmission slave device reception master device transmission and master device reception This is done by software configuration Slave device transmission Set the I2SMSEL bit and OPERSEL 1 0 00 t...

Page 170: ...ntrolled by the audio protocol selector Besides the user can also select the number of data bits and channel bits by software Meanwhile the audio protocol selector manages the WS controller output or...

Page 171: ...e number of DMA transfer is 1 Only the last 16 bits are valid while the first 16 bit data are forced to 0 by hardware LSB aligned standard 24 bit data and 32 bit channel The number of data bits is dif...

Page 172: ...002 561 0 03 195 1 7992 327 0 10 200 Yes 192000 3 0 130208 3 32 18 3 0 130208 3 32 18 200 Yes 96000 4 0 97656 25 1 73 4 0 97656 25 1 73 200 Yes 48000 8 0 48828 13 1 73 8 0 48828 13 1 73 200 Yes 44100...

Page 173: ...00 35 0 32142 86 0 45 17 1 32142 86 0 45 72 No 22050 51 0 22058 82 0 04 25 1 22058 82 0 04 72 No 16000 70 1 15957 45 0 27 35 0 16071 43 0 45 72 No 11025 102 0 11029 41 0 04 51 0 11029 41 0 04 72 No 80...

Page 174: ...ress as the source of DMA transfer in the DMA control register Data will be loaded from the SPI_DT register to the programmed destination after reception request is received by DMA Configure the total...

Page 175: ...eration mode selector Configure audio protocol selector Configure I2S_SCK controller Configure DMA transfer if necessary Set the I2SEN bit to enable I2S Follow above steps to configure the I2SxEXT For...

Page 176: ...als The SPI interface cannot be used as both I2 S and SPI simultaneously so the I2 S shares some pins with the SPI described as follows SD Serial data mapped on the MOSI pin for bidirectional data tra...

Page 177: ...tion in Single line bidirectional half duplex mode 0 Receive only mode 1 Transmit only mode Bit 13 CCEN 0x0 rw RC calculation enable 0 Disabled 1 Enabled Bit 12 NTC 0x0 rw Transmit CRC next When this...

Page 178: ...512 1001 Divided by 1024 Bit 2 MSTEN 0x0 rw Master enable 0 Disabled Slave 1 Enabled Master Bit 1 CLKPOL 0x0 rw Clock polarity Indicates the polarity of clock output in idle state 0 Low level 1 High...

Page 179: ...w error occurs Bit 5 MMERR 0x0 ro Master mode error This bit is set by hardware and cleared by software read write access to the SPI_STS register followed by write operation to the SPI_CTRL1 regitser...

Page 180: ...on CRC8 standard when 16 bit data bit is selected follow CRC16 standard Note This register is only used in SPI mode 13 4 7 SPITxCRC register SPI_TCRC Bit Register Reset value Type Description Bit 15...

Page 181: ...ngth 01 24 bit data length 10 32 bit data length 11 Not allowed Bit 0 I2SCBN 0x0 rw I2 S channel bit num This bit can be configured only when the I2 S is set to 16 bit data otherwise it is fixed to 32...

Page 182: ...1 65535 O 4 O TMR3 only X TMR9 16 Up X 1 65535 X 2 O X X TMR10 TMR11 16 Up X 1 65535 X 1 X X X Timer type Timer Counter bit Count mode PWM output Single pulse output Complementary output Dead time Enc...

Page 183: ...ut control Output control Output control Output control C4OUT C3OUT C2OUT C1OUT Polarity selection edge detector prescaler IS3 IS2 IS1 IS0 C21FP1 TMRx_EXT Trigger control Slave mode controller Encoder...

Page 184: ...the synchronization circuit Figure 14 4 Counting in external clock mode A 30 COUNTER OVFIF TMR_CLK 110 STIS 2 0 Clear CNT_CLK C2IRAW 000 C2IF 2 0 31 32 0 1 2 3 4 Figure 14 5 Block diagram of external...

Page 185: ...4 7 Counter timing with prescaler value changing from 1 to 4 TMR_CLK CK_CNT COUNTER OVFIF DIV 15 0 18 17 19 1A 1B 1C 0 3 00 01 Clear PR 15 0 1C 14 1 3 2 Counting mode The timer TMR2 to TMR5 supports s...

Page 186: ...divided by 4 TMR_CLK CNT_CLK COUNTER OVFIF 0 1 2 3 4 DIV 15 0 32 31 30 32 PR 15 0 Clear Up down counting mode In up down counting mode the counter counts up down alternatively When the counter counts...

Page 187: ...own Up Count on both C1IN and C2IN High Down Up Up Down Low Up Down Down Up Figure 14 12 Example of counter behavior in encoder interface mode encoder mode C 20 21 22 23 24 25 26 27 26 25 24 23 22 21...

Page 188: ...n the TMRx_IDEN register Timer Input XOR function The 3 timer input pins TMRx_CH1 TMRx_CH2 and TMRx_CH3 are connected to the channel 1 selected by setting the C1INSE in the TMRx_CTRL2 register through...

Page 189: ...MREN bit is cleared as soon as the current counting is completed Therefore only one pulse is output When configured as in upcounting mode the configureation must follow the rule CVAL CxDT PR in downco...

Page 190: ...3 2 1 0 1 2 3 COUNTER 31 32 31 30 30 PR 15 0 C1ORAW TMR_CLK 0 DIV 15 0 32 110 C1OCTRL 2 0 3 C1DT 15 0 C1ORAW 0 0 CIDT 15 0 1 C1ORAW 32 C1DT 15 0 Figure 14 19 One pulse mode 0 1 2 3 4 5 6 40 41 42 43...

Page 191: ...tion The timers are linked together internnaly for timer synchronization Master timer is selected by setting the PTOS 2 0 bit Slave timer is selected by setting the SMSEL 2 0 bit Slave mode include Sl...

Page 192: ...can be configured in different master and slave modes respectively The combination of both them can be used for various purposes Figure 14 24 provides an example of interconnection between master tim...

Page 193: ...imer Figure 14 25 Using master timer to start slave timer 0 1 2 3 31 32 0 1 31 32 0 1 2 3 31 COUNTER 0 1 2 3 32 PR 15 0 TMREN TMR_CLK 0 DIV 15 0 32 22 PR 15 0 Overflow event 1 21 22 0 1 2 3 21 COUNTER...

Page 194: ...E in the DEBUG module 14 1 4 TMRx registers These peripheral registers must be accessed by word 32 bits All TMRx register are mapped into a 16 bit addressable space Table 14 4 TMRx register map and re...

Page 195: ...o way counting mode1 count up and down alternately the output flag bit is set only when the counter counts down 10 Two way counting mode2 count up and down alternately the output flag bit is set only...

Page 196: ...t 2 0 Reserved 0x0 resd Kept at its default value 14 1 4 3 Slave timer control register TMRx_STCTRL Bit Register Reset value Type Description Bit 15 ESP 0x0 rw External signal polarity 0 High or risin...

Page 197: ...x0 rw Subordinate TMR mode selection 000 Slave mode is disabled 001 Encoder mode A 010 Encoder mode B 011 Encoder mode C 100 Reset mode Rising edge of the TRGIN input reinitializes the counter 101 Sus...

Page 198: ...Rx_ISTS Bit Register Reset value Type Description Bit 15 13 Reserved 0x0 resd Kept at its default value Bit 12 C4RF 0x0 rw0c Channel 4 recapture flag Please refer to C1RF description Bit 11 C3RF 0x0 r...

Page 199: ...egister An overflow event is generated when OVFG 1 in the TMRx_SWEVE register An overflow event is generated when the counter CVAL is reinitialized by a trigger event 14 1 4 6 Software event register...

Page 200: ...sconnected C1ORAW is disconnected from C1OUT 001 C1ORAW is high when TMRx_CVAL TMRx_C1DT 010 C1ORAW is low when TMRx_CVAL TMRx_C1DT 011 Switch C1ORAW level when TMRx_CVAL TMRx_C1DT 100 C1ORAW is force...

Page 201: ...selection of input pin when C2EN 0 00 Output 01 Input C2IN is mapped on C2IRAW 10 Input C2IN is mapped on C1IRAW 11 Input C2IN is mapped on STCI This mode works only when the internal trigger input i...

Page 202: ...ernal trigger input is selected by STIS Bit 7 C3OSEN 0x0 rw Channel 3 output switch enable Bit 6 4 C3OCTRL 0x0 rw Channel 3 output control Bit 3 C3OBEN 0x0 rw Channel 3 output buffer enable Bit 2 C3OI...

Page 203: ...o C1EN description Bit 7 6 Reserved 0x0 resd Kept at its default value Bit 5 C2P 0x0 rw Channel 2 polarity Pleaser refer to C1P description Bit 4 C2EN 0x0 rw Channel 2 enable Pleaser refer to C1EN des...

Page 204: ...rw Channel 1 data register When TMR2 or TMR5 enables plus mode the PMEN bit in the TMR_CTRL1 register the C1DT is expanded to 32 bits Bit 15 0 C1DT 0x0000 rw Channel 1 data register When the channel 1...

Page 205: ...R2 or TMR5 enables plus mode the PMEN bit in the TMR_CTRL1 register the C4DT is expanded to 32 bits Bit 15 0 C4DT 0x0000 rw Channel 4 data register When the channel 4 is configured as input mode The C...

Page 206: ...hannels for input capture output compare PWM generation and one pulse mode output Synchronization control between master and slave timers Interrrupt is generated at overflow event trigger event and ch...

Page 207: ...CK_INT By default the CK_INT divided by the prescaler is used to drive the counter to start counting Figure 14 29 Control circuit with CK_INT divided by 1 CK_INT TMREN COUNTER 12 11 13 14 15 16 00 01...

Page 208: ...responding timer in a device the corresponding trigger signal ISx is not present Figure 14 32 Counter timing with prescaler value changing from 1 to 4 TMR_CLK CK_CNT COUNTER OVFIF DIV 15 0 18 17 19 1A...

Page 209: ...input signals Figure 14 35 Input output channel 1 main circuit APB bus MCU peripheral interface Channel preload register Channel shadow register C1DT Input mode IC1PS C1EN C1SWTR TMR1_SWEVT Capture Co...

Page 210: ...ured to output one PWM signal In this case the period of the output signal is configured by the TMRx_PR register and the duty cycle by the CxDT register The counter value is compared with the value of...

Page 211: ...one pulse PWM mode B The counter only counts only one cycle and the output signal sents only one pulse Figure 14 38 C1ORAW toggles when counter value matches the C1DT value 0 1 2 3 31 32 0 1 2 3 31 3...

Page 212: ...IF 100 SMSEL 2 0 Slave mode Suspend mode In this mode the counter is controlled by a selected trigger input The counter starts counting when the trigger input is high and stops as soon as the trigger...

Page 213: ...ontrol register1 TMR9_CTRL1 Bit Register Reset value Type Description Bit 15 10 Reserved 0x00 resd Kept at its default value Bit 9 8 CLKDIV 0x0 rw Clock divider 00 Normal 01 Divided by 2 10 Divided by...

Page 214: ...ve mode is disabled 001 Encoder mode A 010 Encoder mode B 011 Encoder mode C 100 Reset mode Rising edge of the TRGIN input reinitializes the counter 101 Suspend mode The counter starts counting when t...

Page 215: ...is configured as input mode This bit is set by hardware on a capture event It is cleared by software or read access to the TMRx_C1DT 0 No capture event occurs 1 Capture event is generated If the chan...

Page 216: ...ation This field is used to define the direction of the channel 2 input or output and the selection of input pin when C2EN 0 00 Output 01 Input C2IN is mapped on C2IRAW 10 Input C2IN is mapped on C1IR...

Page 217: ...N is mapped on C2IRAW 11 Input C1IN is mapped on STCI This mode works only when the internal trigger input is selected by STIS Input capture mode Bit Register Reset value Type Description Bit 15 12 C2...

Page 218: ...x00 resd Kept at its default value Bit 7 C2CP 0x0 rw Channel 2 complementary polarity Pleaser refer to C1P description Bit 6 Reserved 0x0 resd Kept at its default value Bit 5 C2P 0x0 rw Channel 2 pola...

Page 219: ...cription Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 0 C1DT 0x0000 rw Channel 1 data register When the channel 1 is configured as input mode The C1DT is the CVAL value stored by th...

Page 220: ...esd Kept at its default value Bit 9 8 CLKDIV 0x0 rw Clock divider 00 Normal 01 Divided by 2 10 Divided by 4 11 Reserved Bit 7 PRBEN 0x0 rw Period buffer enable 0 Period buffer is disabled 1 Period buf...

Page 221: ...el 1 is configured as input mode This bit is set by hardware on a capture event It is cleared by software or read access to the TMRx_C1DT 0 No capture event occurs 1 Capture event is generated If the...

Page 222: ...TMRx_C1DT TMRx_CVAL else low OWCDIR 1 C1ORAW is low once TMRx_ C1DT TMRx_CVAL else high 111 PWM mode B OWCDIR 0 C1ORAW is low once TMRx_ C1DT TMRx_CVAL else high OWCDIR 1 C1ORAW is high once TMRx_ C1...

Page 223: ...f f 16 N 6 0100 f f 2 N 6 1100 f f 16 N 8 0101 f f 2 N 8 1101 f f 32 N 5 0110 f f 4 N 6 1110 f f 32 N 6 0111 f f 4 N 8 1111 f f 32 N 8 Bit 3 2 C1IDIV 0x0 rw Channel 1 input divider This field defines...

Page 224: ...bled CxOUT 0 1 CxOUT CxORAW polarity Note The state of the external I O pins connected to the standard CxOUT channel depends on the CxOUT channel state and the GPIO and IOMUX registers 14 2 5 7 Counte...

Page 225: ...overflow event trigger event break signal input and channel event Support TMR burst DMA transfer Figure 14 44 Block diagram of advanced control timer Input filter C2IFP1 C1IFP1 XOR Prescaler Output c...

Page 226: ...ock diagram of external clock mode A EXT C1IFP2 C1IFP1 C1INC ISx CK_DIV Trigger select Slave mode control External clock control CI1RAW Filter Edge detector C2IF_Rising C2IF_Falling Polarity selection...

Page 227: ...with prescaler value changing from 1 to 4 TMR_CLK CK_CNT COUNTER OVFIF DIV 15 0 18 17 19 1A 1B 1C 0 3 00 01 Clear PR 15 0 1C 14 3 3 2 Counting mode The advanced control timer consists of a 16 bit cou...

Page 228: ...4 DIV 15 0 32 31 30 32 PR 15 0 Clear Up down counting mode In up down counting mode the counter counts up down alternatively When the counter counts from the value programmed in the TMRx_PR register...

Page 229: ...cates the direction of the counter as shown in the table below Table 14 12 Counting direction versus encoder signals Active edge Level on opposite signal C1INFP1 to C2IN C2INFP2 to C1IN C1INFP1 signal...

Page 230: ...ted if the CxIEN bit and CxDEN bit are enabled If the selected trigger signal is detected when the CxIF is set the CxRF is set To capture the rising edge of C1IN input following the configuration proc...

Page 231: ...the CxDT register The counter value is compared with the value of the TMRx_CxDT register and the corresponding level signal is sent according to the counting direction For more information on PWM mod...

Page 232: ...The counter only counts only one cycle and the output signal sents only one pulse Figure 14 61 C1ORAW toggles when counter value matches the C1DT value 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 3...

Page 233: ...3 4 5 6 7 8 9 A B C D 0 1 2 3 COUNTER CxOSEN 7 CxDT EXT CxORAW Dead time insertion The channel 1 to 3 of the advanced control timers contains a set of reverse channel output This function is enabled...

Page 234: ...mains high When complementary outputs are used The outputs are first put in reset state that is inactive state depending on the polarity This is done asynchronously so that it works even if no clock i...

Page 235: ...by setting the SMSEL 2 0 bit Slave modes include Slave mode Reset mode The counter and its prescaler can be reset by a selected trigger signal An overflow event can be generated when OVFS 0 Figure 14...

Page 236: ...0 1 2 3 4 8 32 OVFIF Please refer to 14 1 3 5 fore more details 14 3 3 7 Debug mode When the microcontroller enters debug mode CortexTM M4F core halted the TMRx counter stops counting by setting the T...

Page 237: ...g mode depending on the OWCDIR bit 01 Two way counting mode1 count up and down alternately the output flag bit is set only when the counter counts down 10 Two way counting mode2 count up and down alte...

Page 238: ...election 0 CH1 pin is connected to C1IRAW input 1 The XOR result of CH1 CH2 and CH3 pins is connected to C1IRAW input Bit 6 4 PTOS 0x0 rw Master TMR output selection This field is used to select the T...

Page 239: ...y after it has been generated N times 0000 No filter sampling by f 0001 f f _ N 2 0010 f f _ N 4 0011 f f _ N 8 0100 f f 2 N 6 0101 f f 2 N 8 0110 f f 4 N 6 0111 f f 4 N 8 1000 f f 8 N 6 1001 f f 8 N...

Page 240: ...ue Type Description Bit 15 Reserved 0x0 resd Kept at its default value Bit 14 TDEN 0x0 rw Trigger DMA request enable 0 Disabled 1 Enabled Bit 13 HALLDE 0x0 rw HALL DMA request enable 0 Disabled 1 Enab...

Page 241: ...apture is detected 1 Capture is detected Bit 8 Reserved 0x0 resd Default value Bit 7 BRKIF 0x0 rw0c Break interrupt flag This bit indicates whether the break input is active or not It is set by hardwa...

Page 242: ...default value Bit 7 BRKSWTR 0x0 wo Break event triggered by software This bit is set by software to generate a break event 0 No effect 1 Generate a break event Bit 6 TRGSWTR 0x0 rw Trigger event trig...

Page 243: ...C2IN is mapped on C2IRAW 10 Input C2IN is mapped on C1IRAW 11 Input C2IN is mapped on STCI This mode works only when the internal trigger input is selected by STIS register Bit 7 C1OSEN 0x0 rw Channe...

Page 244: ...is selected by STIS Input capture mode Bit Register Reset value Type Description Bit 15 12 C2DF 0x0 rw Channel 2 digital filter Bit 11 10 C2IDIV 0x0 rw Channel 2 input divider Bit 9 8 C2C 0x0 rw Chan...

Page 245: ...input mode Attention must be given to the fact that the same bit can have different functions in input mode and output mode Output compare mode Bit Register Reset value Type Description Bit 15 C4OSEN...

Page 246: ...rks only when the internal trigger input is selected by STIS 14 3 4 9 Channel control register TMRx_CCTRL Bit Register Reset value Type Description Bit 15 14 Reserved 0x0 resd Kept its default value B...

Page 247: ...e timer CxOUT 0 Cx_EN 0 CxORAW polarity CxCOUT CxORAW xor CxCP CxCEN 1 0 1 0 CxORAW polarity CxOUT CxORAW xor CxP Cx_EN 1 Output disabled no driven by the timer CxCOUT 0 CxCEN 0 0 1 1 CxORAW polarity...

Page 248: ...ister when an overflow event occurs 14 3 4 12 TMR1 and TMR8 period register TMRx_PR Bit Register Reset value Type Description Bit 15 0 PR 0x0000 rw Period value This defines the period value of the TM...

Page 249: ...e C3OBEN bit and the corresponding output is generated on C3OUT as configured 14 3 4 17 TMR1 and TMR8 channel 4 data register TMRx_C4DT Bit Register Reset value Type Description Bit 15 0 C3DT 0x0000 r...

Page 250: ...Write protection is OFF 01 Write protection level 3 and the following bits are write protected TMRx_BRK DTC BRKEN BRKV and AOEN TMRx_CTRL2 CxIOS and CxCIOS 10 Write protection level 2 The following bi...

Page 251: ...ytes 10001 18 bytes Bit 7 5 Reserved 0x0 resd Kept at its default value Bit 4 0 ADDR 0x00 rw DMA transfer address offset ADDR is defined as an offset starting from the address of the TMRx_CTRL1 regist...

Page 252: ...watchdog block diagram EN 7 bit window value WIN 6 0 Prescaler 1 2 4 8 7 bit counter CNT 6 0 PCLK 4096 CNT 0x40 reset reload at CNT WIN reset To prevent a system reset while reloading the counter valu...

Page 253: ...CortexTM M4F core halted the WWDT counter stops counting by setting the WWDT_PAUSE in the DEBUG module 15 5WWDT registers These peripheral registers must be accessed by word 32 bits Table 15 2 WWDT r...

Page 254: ...ided by 8192 10 PCLK1 divided by 16384 11 PCLK1 divided by 32768 Bit 6 0 WIN 0x7F rw Window value if the counter is reloaded while its value is greater than the window register value a reset is genera...

Page 255: ...un after a power on reset WDT reset conditions When the counter value of the WDT counts down to 0 a WDT reset is generated Thus the WDT_CMD register must be written with the value 0xAAAA at regular in...

Page 256: ...Min timeout ms RLD 11 0 0x000 Max timeout ms RLD 11 0 0xFFF 4 0 0 1 409 6 8 1 0 2 819 2 16 2 0 4 1638 4 32 3 0 8 3276 8 64 4 1 6 6553 6 128 5 3 2 13107 2 256 6 or 7 6 4 26214 4 16 4Debug mode When the...

Page 257: ...vided by 256 The write protection must be unlocked in order to enable write access to the register The register can be read only when DIVF 0 16 5 3 Reload register WDT_RLD Reset in Standby mode Bit Re...

Page 258: ...B1 interface It is used to interface with the APB1 bus and battery powered domain for the configuration and read access of the RTC registers RTC counter logic It consists of a 20 bit prescaler and a 3...

Page 259: ...ttery powered domain by setting BPWEN 1 in the PWC_CTRL register Configuring DIV CNT and ALA registers To enable write operation to these registers the first step is to enter configuration mode CFGEN...

Page 260: ...nterrupt the RTC alarm interrupt must be enabled to use the RTCAlarm_IRQn vector and the EXINT 17 is configured as interrupt mode at the same time To wake from DEEPSLEEP mode using the RTC alarm event...

Page 261: ...TC_DIVL 0x0C 0x8000 RTC_DIVCNTH 0x10 0x0000 RTC_DIVCNTL 0x14 0x8000 RTC_CNTH 0x18 0x0000 RTC_CNTL 0x1C 0x0000 RTC_TAH 0x20 0xFFFF RTC_TAL 0x24 0xFFFF 17 5 1 RTC control register high RTC_CTRLH Bit Reg...

Page 262: ...the user must wait until this bit is set 0 RTC registers not updated 1 RTC registers updated Bit 2 OVFF 0x0 rw0c Overflow flag This bit is set when the counter overflows An interrupt is generarted if...

Page 263: ...ter Reset value Type Description Bit 15 0 CNT 0x0000 rw RTC counter value This field is used to configure or read the high part of the RTC counter value RTC counter value register low RTC_CNTL Bit Reg...

Page 264: ...accordingly If the tamper interrupt is enabled an interrupt will be generated with the TPIF bit being set to 1 In addition the BPR also has RTC calibration feature so that the RTC clock can be slowed...

Page 265: ..._DT28 0x84 0x0000 BPR_DT29 0x88 0x0000 BPR_DT30 0x8C 0x0000 BPR_DT31 0x90 0x0000 BPR_DT32 0x94 0x0000 BPR_DT33 0x98 0x0000 BPR_DT34 0x9C 0x0000 BPR_DT35 0xA0 0x0000 BPR_DT36 0xA4 0x0000 BPR_DT37 0xA8...

Page 266: ...requency divided by 64 on the TAMPER pin The TAMPER function can not be used when the calibration clock output is enabled Note This bit is cleared when the VDD supply is powered off Bit 6 0 CALVAL 0x0...

Page 267: ...ag This bit is set when a tamper event is detected 0 No tamper event 1 A tamper event is detected Note A tamper event will reset the BPR_DTx registers Do not write the BPR_DTx registers when TPEF 1 Bi...

Page 268: ...hannels with different priority Regular channels and injected channels both have their own trigger detection circuit Each channel can independently define its own sampling time Conversion sequence man...

Page 269: ...ment Preempted channels Ordinary channels Address Data bus Data management GPIO CCE flag PCCE flag ADC interrupt to NVIC DMA request VSSA VDDA V REF VREF Trigger detection VMOR flag CCEIEN PCCEIEN VMO...

Page 270: ...eempted channel conversion the ordinary channel conversion won t start until the end of the preempted channel conversion Program the ADC_Inx into the ordinary channel sequence ADC_OSQx and the preempt...

Page 271: ...CDIV bit in the CRM_CFG register The ADCCLK is derived from PCLK2 frequency division Note ADCCLK must be less than 28 MHz Then set the ADCEN bit in the ADC_CTRL2 register to supply the ADC and wait un...

Page 272: ...sion is triggered by preempted ones When the OCTEN or PCTEN bit is set in the ADC_CTRL2 register only the rising edge of the trigger source can start the conversion The conversion can be triggered by...

Page 273: ...s A single conversion time is calculated with the following formula A single one conversion tiem ADCCLK period sampling time 12 5 Example If the CSPTx selects 1 5 period one conversion requires 1 5 12...

Page 274: ...y at the end of the conversion of the ordinary group Figure 19 5 shows an example of the behavior when the automatic preempted group conversion mode works with the ordinary group Figure 19 5 Preempted...

Page 275: ...ed group In this mode the ordinary group conversion sequence length OCLEN bit in the ADC_OSQ1 register is divided into a sub group with only one channel A single one trigger event will convert the cha...

Page 276: ...ts the converted data of the preempted group When the OCDMAEN is set in the ADC_CTRL2 register the ADC will issue DMA requests each time when the ADC_OTD register is updated ADC1 has its own DMA chann...

Page 277: ...ment In Master Slave mode the data of ordinary channels is also stored in the ADC_ODT register of ADC1 As long as the OCDMAEN is set in the ADC1_CTRL2 register the ADC1 DMA channel is used to generate...

Page 278: ...ADC2_IN4 ADC2_IN3 CCE and PCCE flag set ADC1 preempted trigger CCE and PCCE flag set Combined regular preempted simultaneous conversion mode MSSEL bit in the ADC_CTRL1 register is used to select comb...

Page 279: ...te The preempted group conversion is not allowed in this mode Figure 19 13 Fast shift mode on regular group ADC2 ADC1 ADC1_IN3 ADC1_IN3 ADC1_IN3 ADC1 CCE flag set 7 ADCCLK Sampling Conversion ADC1 ord...

Page 280: ...nable simultaneous conversion of the preempted group by master slave If the regular group conversion is interrupted by the preempted group the regular group conversion is stopped and resumes from ADC2...

Page 281: ...inary or preempted group Bit 0 VMOR 0x0 rw0c Voltage monitoring out of range flag This bit is set by hardware and cleared by software writing 0 0 Voltage is within the value programmed 1 Voltage is ou...

Page 282: ...roup automatic conversion disabled 1 Preempted group automatic conversion enabled Bit 9 VMSGEN 0x0 rw Voltage monitoring enable on a single channel 0 Disabled Voltage monitoring enabled on all channel...

Page 283: ...ordinary channels conversion 0 Trigger mode disabled for ordinary channels conversion 1 Trigger mode enabled for ordinary channels conversion Bit 25 Bit 19 17 OCTESEL 0x0 rw Trigger event select for...

Page 284: ...or calibration completed 1 Enable calibration or calibration is in process Bit 1 RPEN 0x0 rw Repition mode enable 0 Repition mode disabled When SQEN 0 a single conversion is done each time when a tri...

Page 285: ...cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cycles Bit 17 15 CSPT15 0x0 rw Sample time selection of channel ADC_IN15 000 1 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles...

Page 286: ...239 5 cycles 19 6 5 ADC sampling time register 2 ADC_SPT2 Accessible word Bit Register Reset value Type Description Bit 31 30 Reserved 0x0 resd Kept at its default value Bit 29 27 CSPT9 0x0 rw Sample...

Page 287: ...0x0 rw Sample time selection of channel ADC_IN4 000 1 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cycles Bit 11 9 CSPT3 0x0 rw Sam...

Page 288: ...le word Bit Register Reset value Type Description Bit 31 12 Reserved 0x00000 resd Kept at its default value Bit 11 0 VMHB 0xFFF rw Voltage monitoring high boundary 19 6 8 ADC voltage monitor low thres...

Page 289: ...nary sequence register 3 ADC_OSQ3 Accessible word Bit Register Reset value Type Description Bit 31 30 Reserved 0x0 resd Kept at its default value Bit 29 25 OSN6 0x00 rw Number of 6th conversion in ord...

Page 290: ...4 5 19 6 13ADC preempted data register x ADC_PDTx x 1 4 Accessible word Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 0 PDTx 0x0000 rw Conve...

Page 291: ...mask mode FIFO overrun management Time triggered communication mode 16 bit timers Time stamp on transmission 20 3Baud rate configuration The nominal bit time of the CAN bus consists of three parts as...

Page 292: ...segment 1 and big segment 2 simulatenously During the actual transmission each bit of the CAN nodes has certain phase error due to the oscillator drift transmission delay among the network nodes and...

Page 293: ...eld 2 7 EOF ACK RTR r0 IDE SOF Data frame or remote frame Error frame Inter frame space or overload frame Error flag Error echo Error delimiter 6 6 8 Data frame or remote frame Intermission Suspend tr...

Page 294: ...rrupt generation TM0TCF 1 TM1TCF 1 TM2TCF 1 TCIEN 1 TX_INT Figure 20 4 Receive interrupt 0 generation RF0MN 00 RFF0MIEN 1 RF0FF 1 RF0FIEN 1 RF0OF 1 RF0OIEN 1 RX0_INT Figure 20 5 Receive interrupt 1 ge...

Page 295: ...AN_FBWCFG and CAN_FRF registers can be modified only when FCS 1 The CAN_FiFBx register can be modified only when FCS 1 or FAENx 0 20 6Function overview 20 6 1 General functional description As the num...

Page 296: ...ion and filter values can be initialized in non Frozen mode When the CAN controller is in Frozen mode message reception and transmission are both disabled Switch from Frozen mode to Communication mode...

Page 297: ..._FBWCFG register 32 bit fliter register CAN_FiFBx includes the SID 10 0 EID 17 0 IDT and RTR bits CAN_FiFB1 31 21 CAN_FiFB1 20 3 CAN_FiFB1 2 0 CAN_FiFB2 31 21 CAN_FiFB2 20 3 CAN_FiFB2 2 0 SID 10 0 EID...

Page 298: ...0 bit in the CAN_RFCx register The distribution of the filter number does not take into account the activation state of the filter banks The table below shows examples of filter numbering Filter bank...

Page 299: ...setting the FBWSELx bit in the CAN_FBWCFG register The filter x is associated with FIFO0 or FIFO1 by writing the FRFSELx bit in the CAN_FRF register The filter banks x are activated by setting FAENx...

Page 300: ...and TMxEF bits in the CAN_TSTS register are used to indicate transmit status and error status TMxTCF bit Transmission complete flag indicating that the data transmission is complete when TMxTCF 1 TMxT...

Page 301: ...a frame of message and the RFxR is set in the CAN_RFx register one FIFO mailbox is released and RFxMN 1 0 bit is descremented by one in the CAN_RFx register Receive FIFO status RFxMN 1 0 RFxFF and RF...

Page 302: ...1 When AEBOEN 0 in the CAN_MCTRL register in communication mode the software requests to enter Frozen mode and exit Frozen mode and CAN will then resume from bus off state after 128 occurences of 11...

Page 303: ...7 1 CAN control and status registers 20 7 1 1 CAN master control register CAN_MCTRL Bit Register Reset value Type Description Bit 31 17 Reserved 0x0000 resd Kept at its default value Bit 16 PTD 0x1 rw...

Page 304: ...ission enable when sending fails enable 0 Retransmission is enabled 1 Retransmission is disabled Bit 3 MDRSEL 0x0 rw Message discard rule select when overflow 0 The previous message is discarded 1 The...

Page 305: ...bit is set by hardware only when EDZIEN 1 and the CAN enters Sleep mode Whe set this bit will generate a status change interrupt This bit is cleared by software writing 1 to itself or by hardware when...

Page 306: ...ption Bit 31 TM2LPF 0x0 ro Transmit mailbox 2 lowest priority flag 0 Mailbox 2 is not given the lowest priority 1 Lowest priority This indicates that more than one mailboxes are pending for transmissi...

Page 307: ...s bit is set when the mailbox 2 transmission failed due to an arbitration lost It is cleared by software writing 1 or by hardware at the start of the next transmission Bit 17 TM2TSF 0x0 rw1c Transmit...

Page 308: ...by software writing 1 or by hardware when a new transmission request is received Clearing this bit will clear the TSMF1 ALMF1 and TEMF1 bits of mailbox 1 Bit 7 TM0CT 0x0 rw1s Transmit mailbox 0 cancel...

Page 309: ...CF 0x0 rw1c Transmit mailbox 0 transmission completed flag 0 Transmission is in progress 1 Transmission is completed Note This bit is set by hardware when the transmission abort request on mailbox 0 h...

Page 310: ...is full Note This bit is set by hardware when three messages are pending in the FIFO 0 It is cleared by software by writing 1 Bit 2 Reserved 0x0 resd Kept at its default value Bit 1 0 RF0MN 0x0 ro Re...

Page 311: ...t 17 EDZIEN 0x0 rw Enter doze mode interrupt enable 0 Enter sleep mode interrupt disabled 1 Enter sleep mode interrupt enabled Note EDZIF flag bit corresponds to this interrupt An interrupt is generat...

Page 312: ...0 FIFO 1 receive message interrupt disabled 1 FIFO 1 receive message interrupt enabled Note The flag bit of this interrupt is RF1MN bit so an interrupt is generated when this bit and RF1MN bit are se...

Page 313: ...e according to the error condition detected on the CAN bus It is cleared by hardware when a message has been transmitted or received successfully If the error code 7 is not used by hardware this field...

Page 314: ...11 0 BRDIV 0x000 rw Baud rate division tq BRDIV 11 0 1 x tPCLK Note This field defines the length of a time unit tq 20 7 2 CAN mailbox registers This section describes the registers of the transmit a...

Page 315: ...0 No effect 1 Transmit request Note This bit is cleared by hardware when the transmission has been completed The mailbox becomes empty 20 7 2 2 Transmit mailbox data length and time stamp register CA...

Page 316: ...eive mailbox registers are read only Bit Register Reset value Type Description Bit 31 21 RFSID RFEID 0xXXX ro Receive FIFO standard identifier or receive FIFO extended identifier Note This field defin...

Page 317: ...controlled by software completely Bit Register Reset value Type Description Bit 31 1 Reserved 0x160E0700 resd Kept at its default value Bit 0 FCS 0x1 rw Filter configuration switch 0 Disabled Filter b...

Page 318: ...esponds to a filter bank 0 Disabled 1 Enabled 20 7 3 6 CAN filter bank i filter bit register CAN_ FiFBx i 0 13 x 1 2 Note There are 14 filter banks i 0 13 Each filter bank consists of two 32 bit regis...

Page 319: ...ock has two sources HICK 48M When the HICK 48M clock is used as a USB control clock it is recommended to enable ACC feature Divided by PLL The PLL output frequency must ensure that the USBDIV see the...

Page 320: ...and the USBFS module can access to the buffer at the same time The buffer size can be automatically adjusted according to the CAN status Table 21 1 lists its mapping address and size Table 21 1 Buffe...

Page 321: ...t the APB1 bus can write only two byte data to a packet buffer each time For this reason 8 consecutive write accesses are required when a 16 byte data is to be written 21 3 4 Double buffered endpoints...

Page 322: ...r to disable SOF detection and the statistic power consumtion of the USB physical transceiver Resume refers to a process when the USB device returns from a suspend state to a normal state When the USB...

Page 323: ...S 0x0 tog Rx Data Toggle DAT0 DATA1 Synchronization This is not ISO transfer This bit indicates that the current transaction is DATA0 DATA1 0 DATA0 1 DATA1 Bit 13 12 RXSTS 0x0 tog Rx Status This field...

Page 324: ...tatus in response to the IN transaction of the host There are four states DISABLE NAK STALL ACK 00 DISABLED endpoint ignores all transmission requests 01 STALL endpoint responds to all transmission re...

Page 325: ...Reset 0 Software clears reset 1 Software resets usb core and a reset interrupt is generate 21 5 3 USBFS interrupt status register USBFS_INTSTS Bit Register Reset value Type Description Bit 15 TC 0x0...

Page 326: ...SOF packet lost It is cleared by hardware at the reception of an SOF transaction Bit 10 0 SOFNUM 0xXXX ro Start of Frame number Indicates the current SOF frame number 21 5 5 USBFS device address regi...

Page 327: ...SBFS reception buffer first address register USBFS_RnADDR Bit Register Reset value Type Description Bit 15 1 RnADDR 0xXXXX rw Reception buffer first address This field indicates the start address of t...

Page 328: ...n function Center frequency precision 0 25 Status detection flags Calibration ready flag Error detection flags Reference signal lost error flag Two interrupt source flag Calibration ready flag Referen...

Page 329: ...hich can be calibrated to 8MHz 0 25 The HICK frequency can be adjusted by 20kHz design value each time when the CRM_HICKTRIM value changes USB_SOF USB Start of Frame signal given by the USB device Its...

Page 330: ...s return algorithm C1 7980 C3 8020 C2 8000 From the above figure auto calibration function will adjust the HICKCAL or HICKTRIM according to the specified step as soon as the condition for trigerring a...

Page 331: ...d so that the HICK frequency can be adjusted to be within a range of 0 5 steps of the center frequency as soon as the CANLON is enabled Under one of the above mentioned circumstances the HICK frequenc...

Page 332: ...only the HICKTRIM is calibrated If the step is incremented or decremented by one the HICKTRIM will be incremented or decremented by one accordingly and the HICK frequency will increase or decrease by...

Page 333: ...0x0000 resd Forced to 0 by hardware Bit 15 0 C1 0x1F2C rw Compare 1 This value is the lower boundary for triggering calibration and its default value is 7980 When the number of clocks sampled by ACC...

Page 334: ...e Interrupt requests Note The SDIO is not compatible with SPI communication mode It supports only one SD SDIO MMC 4 2 card at any one time Communication on the bus is based on command and data transfe...

Page 335: ...esponse Data block crc Data from card to host Data block crc Data block crc Stop command stops data transfer Multiple block read operation Command Figure 23 3 SDIO multiple data block write operation...

Page 336: ...le point to point command Broadcast command applicable to all cards some need responses Addressible command send to the addressible card and response response from the card Memory card defines two typ...

Page 337: ...sfer read write can be done in data block mode or stream mode configured by the TFRMODE bit in the SDIO_DTCTRL register In the data stream mode data is transferred in bytes and without CRC appended to...

Page 338: ...t any time and the card will respond with its status The READY_FOR_DATA status bit indicates whether the car can accept new data or whether the write process in still in progress The host can deselect...

Page 339: ...le before it sents the card lock unlock command The lock unlock command structure is shown below Table 23 1 Lock unlock command structure Byte Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 Reserved set to...

Page 340: ...ELECT_CARD if none is selected previously 2 Define the block length with CMD16 SET_BLOCKLEN to send in the 8 bit card lock unlock mode 8 bit PWD_LEN and the number of bytes of the new password 3 Send...

Page 341: ...esponse sent to all cards and receive responses from all cards simultaneously 3 Addressible command sent to the selected card and no data transfer on the SDIO_D line 4 Addressible data transfer comman...

Page 342: ...EXT_CSD register as a data block CMD9 ac 31 16 RCA 15 0 stuff bits R2 SEND_CSD The selected card sends CSD card specific data through the CMD bus CMD10 ac 31 16 RCA 15 0 stuff bits R2 SEND_CID The sel...

Page 343: ...that follows CMD24 adtc 31 0 data address R1 WRITE_ BLOCK Write a data block of the size set by the CMD16 CMD25 adtc 31 0 data address R1 WRITE_ MULTIPLE BLOCK Continuously write data blocks until th...

Page 344: ...d CMD38 ac 31 0 stuff bits R1b ERASE Erase all previously selected data blocks Table 23 8 I O mode commands CMD index Type Parameter Response format Abbreviation Description CMD39 ac 31 16 RCA 15 regi...

Page 345: ...olled by the transmission bit indicating the direction of transmission card 0 A value denoted by in the tables below stands for a variable entry All responses except the R3 response type are protected...

Page 346: ...MD41 Table 23 13 R3 response Bit 47 46 45 40 39 8 7 1 0 Field width 1 1 6 32 7 1 Value 1 0 111111 111111 1 Description Start bit Transmission bit Reserved OCR register Reserved End bit 23 3 2 2 5 R4 F...

Page 347: ...6 7 1 Value 1 0 000011 1 Description Start bit Tx bit CMD3 RCA 31 16 of a successful card or of the host Card status CRC7 End bit The card status bit 23 8 will be changed when the CMD3 is sent to an I...

Page 348: ...card and MMC V4 2 also use push pull drivers for initialization SDIO_D 7 0 is a bidirectional data channel After initialization the host can change the width of the data bus After reset the SDIO_D0 i...

Page 349: ...d with each SDIO_CK including start bit transfer bit command index defined by the SDIO_CMDCTRL_CMDIDX bit parameters defined by the SDIO_ARG 7 bit CRC and end bit Then receives responses from the card...

Page 350: ...um delay beteen two host commands and NRC the minimum delay between the host command and the card response When the wait state is entered the command timer is enabled if the NCR timeout resonse time t...

Page 351: ...he TFRDIR bit the DCSM enters Wait_S or Wait_R state Data channel state machine DCSM The DCSM has seven states in send and receive mode as shown in the Figure below Figure 23 9 Data channel state mach...

Page 352: ...te the data to the BUF The write pointer is incremented automatically after the end of the wrie operation On the other side a read pointer always points to the current data in the BUF If the receive B...

Page 353: ...ill enter read wait state and drive the SDIO_D2 to 0 after 2 SDIO_CK cycles The data unit starts waiting to receive data from a card the DCSM will not enter read wait even if read wait start is set Th...

Page 354: ...ister Offset Reset value SDIO_PWRCTRL 0x00 0x0000 0000 SDIO_CLKCTRL 0x04 0x0000 0000 SDIO_ARG 0x08 0x0000 0000 SDIO_CMD 0x0C 0x0000 0000 SDIO_RSPCMD 0x10 0x0000 0000 SDIO_RSP1 0x14 0x0000 0000 SDIO_RS...

Page 355: ...7 0 used Bit 10 BYPSEN 0x0 rw Clock divider bypass enable bit This bit is set or cleared by software When disabled the SDIO_CK output signal is driven by the SDIOCLK that is divided according to the C...

Page 356: ...command enabled Bit 10 CCSMEN 0x0 rw Command channel state machine CCSM enable bit This bit is set or cleared by software 0 Command channel state machine disabled 1 Command channel state machine enab...

Page 357: ...63 32 SDIO_RSP4 Unused Card status 31 1 The most significant bit of the card status is always received first The least significant bit of the SDIO_RSP4 register is always 0 23 4 7 SDIO data timer reg...

Page 358: ...topped if the RDWTSTART is set Bit 8 RDWTSTART 0x0 rw Read wait start This bit is set or cleared by software When this bit is set read wait starts when this bit is cleared no ations occurs 0 Read wait...

Page 359: ...end flag bit DTCMPL Bit Register Reset value Type Description Bit 31 25 Reserved 0x00 resd Kept at its default value Bit 24 0 CNT 0x0000000 ro Data count value When this register is read the number of...

Page 360: ...the correspond bit in the SDIO_STS register Bit Register Reset value Type Description Bit 31 23 Reserved 0x000 resd Kept at its default value Bit 22 IOIF 0x0 rw SD I O interface flag clear bit This bi...

Page 361: ...empty interrupt enable This bit is set or cleared by software to enable disable the RxBUF empty interrupt 0 Disabled 1 Enabled Bit 18 TXBUFEIEN 0x0 rw TxBUF empty interrupt enable This bit is set or c...

Page 362: ...ta end interrupt 0 Disabled 1 Enabled Bit 7 CMDCMPLIEN 0x0 rw Command sent interrupt enable This bit is set or cleared by software to enable disable the Command sent interrupt 0 Disabled 1 Enabled Bit...

Page 363: ...DTLEN register see 23 4 8 when the data transfter bit TFREN is set in the SDIO_DTCTRL register If the data length is not word aligned the remaining 1 to 3 bytes are regarded as a word Bit Register Res...

Page 364: ...ue to work In DeepSleep mode HICK oscillator is enabled to feed FCLK and HCLK There are several ID codes inside the MCU which is accessible by the debugger using the DEBUG_IDCODE at address 0xE0042000...

Page 365: ...2 bit Table 24 3 DEBUG register address and reset value Register Offset Reset value DEBUG_IDCODE 0xE004 2000 0xXXXX XXXX DEBUG_CTRL 0xE004 2004 0x0000 0000 24 4 1 DEBUG device ID DEBUG_IDCODE MCU inte...

Page 366: ...e control bit 0 Work normally 1 Timer is disabled Bit 17 TMR8_PAUSE 0x0 rw TMR8 pause control bit 0 Work normally 1 Timer is disabled Bit 16 I2C2_SMBUS_TIMEOUT 0x0 rw I2 C2 pause control bit 0 Work no...

Page 367: ...oscillator HICK Bit 1 DEEPSLEEP_DEBUG 0x0 rw Debug Deepsleep mode control bit 0 In Deepsleep mode all clcoks in the 1 2V domain are disabled When exiting from Deepsleep mode the internal RC oscillator...

Page 368: ...tial release 2022 06 27 2 01 1 Updated the descriptions in Section 11 5 1 Control register1 I2C_CTRL1 2 Updated Figure 14 1 3 Updated the descriptions of bit 0 in Section 19 6 3 ADC control register2...

Page 369: ...ng legal situation in any injudical districts or infringement of any patent copyright or other intellectual property right ARTERY s products are not designed for the following purposes and thus not in...

Reviews:

No comments