ARTERY AT32F413 Series, Reference Manual, Page: 238 / 369

AT32F413 Series Reference Manual
2022.06.27 Page 238 Rev 2.00
1: Disabled
Bit 0 TMREN 0x0 rw
TMR enable
0: Disabled
1: Enabled
14.3.4.2 TMR1 and TMR8 control register2 (TMRx_CTRL2)
Bit Register Reset value Type Description
Bit 15 Reserved 0x0 resd Kept at its default value.
Bit 14
C4IOS 0x0 rw
Channel 4 idle output state
Bit 13
C3CIOS 0x0 rw
Channel 3 complementary idle output state
Bit 12
C3IOS 0x0 rw
Channel 3 idle output state
Bit 11
C2CIOS 0x0 rw
Channel 2 complementary idle output state
Bit 10
C2IOS 0x0 rw
Channel 2 idle output state
Bit 9
C1CIOS 0x0 rw
Channel 1 complementary idle output state
OEN = 0 after dead-time:
0: C1OUTL=0
1: C1OUTL=1
Bit 8
C1IOS 0x0 rw
Channel 1 idle output state
OEN = 0 after dead-time:
0: C1OUT=0
1: C1OUT=1
Bit 7 C1INSEL 0x0 rw
C1IN selection
0: CH1 pin is connected to C1IRAW input
1: The XOR result of CH1, CH2 and CH3 pins is connected
to C1IRAW input
Bit 6: 4 PTOS 0x0 rw
Master TMR output selection
This field is used to select the TMRx signal sent to the
slave timer.
000: Reset
001: Enable
010: Update
011: Compare pulse
100: C1ORAW signal
101: C2ORAW signal
110: C3ORAW signal
111: C4ORAW signal
Bit 3 DRS 0x0 rw
DMA request source
0: Capture/compare event
1: Overflow event
Bit 2
CCFS 0x0 rw
Channel control bit flash selection
This bit only acts on channels that have
complementaryoutput. If the channel contro bits are
buffered:
0: Control bits are updated by setting the HALL bit
1: Control bits are updated by setting the HALL bit or a
rising edge on TRGIN.
Bit 1 Reserved 0x0 resd
Kept at its default value.
Bit 0
CBCTRL 0x0 rw
Channel buffer control
This bit acts on channels that have complementary
output.
0: CxEN, CxCEN and CxOCTRL bits are not buffered.
1: CxEN, CxCEN and CxOCTRL bits are not buffered.