AT32F413
Series Reference Manual
2022.06.27
Page 150
Rev 2.00
and the RDBF is set accordingly. An interrupt is generated if the RDBFIEN is set.
If hardware flow control is selected, the control signal is output on the RTS pin.
During data reception, the USART receiver will detect whether there are errors to occur, including
framing error, overrun error, parity check error or noise error, depending on software configuration, and
whether there are interrupts to generate using the interrupt enable bits.
12.8.2 Receiver configuration
Configuration procedure:
1. USART enalbe: UEN bit is set.
2. Full-
duplex/half-duplex configuration: Refer to
12.2 Full-duplex/half-duplex selector
3. Mode
configuration: Refer to
4. F
rame format configuration: Refer to
12.4 USART frame format and configuration
5. In
terrupt configuration: Refer to
6. Reception using DMA:
If the DMA mode is selected, the DMAREN bit is set, and configure DMA
register accordingly.
7. Baud
rate configuration: Refer to
..
8. Receiver
enable: REN bit is set.
Character repeption:
The RDBF bit is set. It indicates that the content of the shift register is transferred to the RDR
(Receiver Data Register). In other words, data is received and can be read (including its
associated error flags)
An interrupt is generated when the RDBFIEN is set.
The erro flag is set when a framing error, noise error or overrun error is detected during
reception.
In DMA mode, the RDBF bit is set after every byte is received, and it is cleared when the data
register is read by DMA.
In non-DMA mode, the RDBF bit is cleared when read access to the USART_DT register by
software. The RDBF flag can also be cleared by writing 0 to it. The RDBF bit must be cleared
before the end of next frame reception to avoid overrun error.
Break frame reception:
Non-LIN mode: It is handled as a framing error, and the FERR is set. An interrupt is generated if
the corresponding interrupt bit is enabled. Refer to framing error decribed below for details.
LIN mode: It is handled as a break frame, and the BFF bit is set. An interrupt is generated if the
BFIEN is set.
Idle frame reception:
It is handled as a data frame, and the IDLEF bit is set. An interrupt is generated if the IDLEIEN is
set.
When a framing error occurs:
The FERR bit is set.
The USART receiver moves the invalid data from the receive shift register to the receive data
buffer.
In non-DMA mode, both FERR and RDBF are set at the same time. The latter will generate an
interrupt. In DMA mode, an interrupt is generated if the ERRIEN.
When an overrun error occurs:
The ROERR bit is set.
The data in the receive data buffer is not lost. The previous data is still available when the
USART_DT register is read.
The content in the receive shift register is overwritten.Afterwards, any data received will be lost.