AT32F413
Series Reference Manual
2022.06.27
Page 47
Rev 2.00
PLL. Otherwise, once the PLL is enabled, these parameters cannot be changed. The PLL clock signal
is not released until it becomes stable.
Low speed external oscillator (LEXT)
The LEXT oscillator provides two clock sources: LEXT crystal/ceramic resonator and LEXT bypass.
LEXT crystal/ceramic resonator:
The LEXT crystal/ceramic resonator provides a 32.768 KHz low-speed clock source. The LEXT clock
signal is not released until it becomes stable.
LEXT bypass clock
In this mode, an external clock source with a frequency of 32.768 kHzcan be provided. The external
clock signal should be connected to the LEXT_IN pin while the LEXT_OUT remains floating.
Low speed internal RC oscillator (LICK)
The LICK oscillator is clocked by an internal low-speed RC oscillator. The clock frequency is between
30 kHz and 60 kHz. It acts as a low-power clock source that can be kept running in Deepsleep mode
and Standby mode for watchdog and auto-wakeup unit.
The LICK clock signal is not released until it becomes stable.
4.1.2
System clock
After a system reset, the HICK oscillator is selected as system clock. The system clock can make flexible
switch among HICK oscillator, HEXT oscillator and PLL clock. However, a switch from one clock source
to another occurs only if the target clock source becomes stable. When the HICK oscillator is used
directly or indirectly through the PLL as the system clock, it cannot be stopped.
4.1.3
Peripheral clock
Most peripherals use HCLK, PCLK1 or PCLK2 clock. The individual peripherals have their dedicated
clocks.
System Tick timer (SysTick) is clocked by HCLK or HCLK/8.
ADCs are clocked by APB2 divided by 2, 4, 6, 8, 12 or 16.
The timers are clocked by APB1/2. In particular, if the APB prescaler is 1, the timer clock frequency is
equal to that of APB1/2; otherwise, the timer clock frequency is set to double the APB1/2 frequency.
The USB clock source can be switched between HICK and PLL frequency divider. If the HICK is selected
as the clock source, the USB clock should be set as 48 MHz; If the PLL frequency divider is selected as
the clock source, the USB frequency divider provides 48 MHz USBCLK, and thus the PLL needs to be
set as 48*N*0.5 MHz (N=2,3,4,5…)
RTC clock sources: HEXT/128, LEXT oscillator and LICK oscillator. Once the clock source is selected,
it cannot be altered without resetting the battery powered domain. If the LEXT is used as RTC clock, the
RTC is not affected when the VDD is powered off. If the HEXT or LICK is selected as RTC clock, the
RTC state is not guaranteed when both HEXT and LICK are powered off.
Watchdog is clocked by LICK oscillator. If the watchdog is enabled by either hardware option or software
access, the LICK oscillator is forced ON. The clock is provided to the watchdog only after the LICK
oscillator temporization.