AT32F413
Series Reference Manual
2022.06.27
Page 284
Rev 2.00
1111: Timer 8 TRGOUT event
Bit 11
DTALIGN
0x0
rw
Data alignment
0: Right alignment
1: Left alignment
Bit 10: 9
Reserved
0x0
resd
Kept at its default value.
Bit 8
OCDMAEN
0x0
rw
DMA transfer enable of ordinary channels
0: DMA transfer disabled
1: DMA transfer enabled
Note: ADC2 has no DMA function, and thus it cannot
generate a DMA request itself
Bit 7: 4
Reserved
0x0
resd
Kept at its default value.
Bit 3
ADCALINIT
0x0
rw
Initialize A/D calibration
This bit is set by software and cleared by hardware. It is
cleared after the calibration registers are initialized.
0: No initialization occurred or initialization completed
1: Enable initialization or initializationis is ongoing
Bit 2
ADCAL
0x0
rw
A/D Calibration
0: No calibration occurred or calibration completed
1: Enable calibration or calibration is in process
Bit 1
RPEN
0x0
rw
Repition mode enable
0: Repition mode disabled
When SQEN=0, a single conversion is done each time
when a trigger event arrives; when SQEN=1, a group of
conversion is done each timer when a trigger event arrives.
1: Repition mode enabled
When SQEN =0, continuous conversion mode on a single
channel is enabled at each trigger event; when SQEN =1,
continuous conversion mode on a group of channels is
enabled at each trigger event.
Bit 0
ADCEN
0x0
rw
A/D converter enable
0: A/D converter disabled (ADC goes to power-down
mode)
1: A/D converter enabled
Note:
When this bit is in OFF state, write an ON command can
wake up The ADC from power-down mode.
When this bit in ON state, write an ON command
repeatedly while other bits of the register remain
unchanged can start a regular group conversion.
The application should pay attention to the fact that there
is a delay of t
STAB
between power on and start of
conversion.