UG-549
ADuCM310 Hardware Reference Manual
Rev. C | Page 94 of 192
Write Abort Address Register
Address: 0x40018040, Reset: 0x0000000X, Name: FEEWRADDRA
Table 118. Bit Descriptions for FEEWRADDRA
Bits
Bit Name
Description
Reset
Access
[31:0]
WRABORTADDR
If a write is aborted, this register contains the address of the location being
written when the write was aborted. This register has appropriate value if
command abort happened. This register must be read after the command
is aborted and must be read before any other command is given. After
reset, the value is random.
0xx
R
Interrupt Abort Enable Register: Interrupt 31 to Interrupt 0
Address: 0x40018048, Reset: 0x00000000, Name: FEEAEN0
Table 119. Bit Descriptions for FEEAEN0
Bits
Bit Name
Description
Reset
Access
[31:0]
SYSIRQABORTEN
Lower 32 bits of system interrupt abort enable. To allow a system interrupt
to abort a command (write, erase, sign, or mass verify), write a 1 to the
appropriate bit in this register. Each bit corresponds to one interrupt listed
in the interrupt vector table.
0x0
RW
Interrupt Abort Enable Register: Interrupt 54 to Interrupt 32
Address: 0x4001804C, Reset: 0x000000, Name: FEEAEN1
Table 120. Bit Descriptions for FEEAEN1
Bits
Bit Name
Description
Reset
Access
[22:0]
SYSIRQABORTEN
Upper 23 bits of system interrupt abort enable. To allow a system interrupt
to abort a command (write, erase, sign, or mass verify), write a 1 to the
appropriate bit in this register. Each bit corresponds to one interrupt listed
in the interrupt vector table.
0x0
RW
ECC Enable/Disable, Error Response Register
Address: 0x40018064, Reset: 0x00000000, Name: FEEECCCONFIG
This register is key protected; the key (0x5ECCACCE) must be entered in FEEKEY. After writing to FEECCCONFIG, the key is cleared.
Table 121. Bit Descriptions for FEEECCCONFIG
Bits
Bit Name
Description
Reset Access
[31:5] RESERVED
Reserved
0x0
R
[4:3]
ECCCMDINTEN
Interrupt enabled (flash interrupt) when an ECC error occurs during a read.
0x0
RW
00: interrupt is not generated if an ECC error occurs while reading from the flash.
01: interrupt enabled only if a 2-bit error is detected during a read from Flash 0 or Flash 1.
10: interrupt enabled only if a 1-bit error is detected during a read from Flash 0 or Flash 1.
11: interrupt enabled if either a 2-bit error or 1-bit error is detected during a read from Flash 0
or Flash 1.
[2:1]
ECCCMDAHBEN Generates a system exception (bus fault) when an ECC error occurs during a read.
0x0
RW
00: exception is not generated if an ECC error occurs while reading from flash.
01: exception enabled only if a 2-bit error is detected during a read from Flash 0 or Flash 1.
10: exception enabled only if a 1-bit error is detected during a read from Flash 0 or Flash 1.
11: exception enabled if either a 2-bit error or 1-bit error is detected during a read from Flash 0
or Flash 1.
0
ECCDISABLE
Setting this bit to 1 disables ECC. When ECC is disabled, the ECC module is bypassed. When a
read to a flash location is carried out, corresponding to the requested address, LSB 32 or MSB 32 bit
raw-data is returned to the bus.
0x0
RW
