UG-549
ADuCM310 Hardware Reference Manual
Rev. C | Page 134 of 192
SERIAL PERIPHERAL INTERFACES
SPI FEATURES
The
integrates two complete hardware serial peripheral interfaces with the following standard SPI features:
•
Serial clock phase mode and serial clock polarity mode
•
LSB first transfer option
•
Loopback mode
•
Master or slave mode
•
Transfer and interrupt mode
•
Continuous transfer mode
•
Tx/Rx FIFO
•
Interrupt mode, interrupt after one, two, three, or four bytes
•
Rx overflow mode and Tx underrun mode
•
Open-circuit data output mode
•
Full-duplex communications supported (simultaneous transmit/receive)
SPI OVERVIEW
The
integrates two complete hardware serial peripheral interfaces (SPI). SPI is an industry standard, synchronous serial interface
that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex. The two SPIs implemented
on the
can operate to a maximum bit rate of 20 Mbps in both master and slave mode.
The SPI blocks have an additional DMA feature. It has two DMA channels that interface with a µDMA controller of the ARM Cortex-M3
processor. One DMA channel is used for transmit and the other for receive.
SPI OPERATION
The SPI port can be configured for master or slave operation and consists of four pins: MISO, MOSI, SCLK, and CS.
Note that the GPIOs used for SPI communication must be configured in SPI mode before enabling the SPI peripheral, and that the
internal pull-up resistors on the SPI pins must be disabled via the GPxPUL registers when using the SPI.
MISO (Master In, Slave Out) Pin
The MISO pin is configured as an input line in master mode and an output line in slave mode. The MISO line on the master (data in)
must be connected to the MISO line in the slave device (data out). The data is transferred as byte-wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In) Pin
The MOSI pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out)
must be connected to the MOSI line in the slave device (data in). The data is transferred as byte-wide (8-bit) serial data, MSB first.
SCLK (Serial Clock Input/Output) Pin
The master serial clock (SCLK) synchronizes the data being transmitted and received through the MOSI SCLK period. Therefore, a byte
is transmitted/received after eight SCLK periods. The SCLK pin is configured as an output in master mode and as an input in slave mode.
In master mode, the polarity and phase of the clock are controlled by the SPIxCON register, and the bit rate is defined in the SPIxDIV
register as follows:
(
)
SPIxDIV
SPICLK
f
K
SERIALCLOC
+
×
=
1
2
where
SPICLK
is the 80 MHz system clock divided by the factor set in CLKCON1[2:0].
It is possible to disable the clocks to SPI0 and SPI1 separately:
•
CLKCON1[0] = 1 disables the clock to SPI0.
•
CLKCON1[1] = 1 disables the clock to SPI1.
By reducing the clock rate to the SPI blocks, it is possible to reduce the power consumption of the SPI block. The maximum data rate is
20 Mbps.
