UG-549
ADuCM310 Hardware Reference Manual
Rev. C | Page 176 of 192
Wake-Up Field B—Most Significant 16 Bits Register
Address: 0x40002514, Reset: 0x0000, Name: T4WUFB1
Table 259. Bit Descriptions for T4WUFB1
Bits
Bit Name
Description
Reset
Access
[15:0]
T4WUFBH
Wake-Up Field B High. Most significant 16 bits of Wake-Up Field B.
0x0
RW
Wake-Up Field C—Least Significant 16 Bits Register
Address: 0x40002518, Reset: 0x2FFF, Name: T4WUFC0
Table 260. Bit Descriptions for T4WUFC0
Bits
Bit Name
Description
Reset
Access
[15:0]
T4WUFCL
Wake-Up Field C Low. Least significant 16 bits of Wake-Up Field C.
0x2FFF
RW
Wake-Up Field C—Most Significant 16 Bits Register
Address: 0x4000251C, Reset: 0x0000, Name: T4WUFC1
Table 261. Bit Descriptions for T4WUFC1
Bits
Bit Name
Description
Reset
Access
[15:0]
T4WUFCH
Wake-Up Field C High. Most significant 16 bits of Wake-Up Field C.
0x0
RW
Wake-Up Field D—Least Significant 16 Bits Register
Address: 0x40002520, Reset: 0x3FFF, Name: T4WUFD0
Table 262. Bit Descriptions for T4WUFD0
Bits
Bit Name
Description
Reset
Access
[15:0]
T4WUFD0
Wake-Up Field D Low. Least significant 16 bits of Wake-Up Field C.
0x3FFF
RW
Wake-Up Field D—Most Significant 16 Bits Register
Address: 0x40002524, Reset: 0x0000, Name: T4WUFD1
Table 263. Bit Descriptions for T4WUFD1
Bits
Bit Name
Description
Reset
Access
[15:0]
T4WUFDH
Wake-Up Field D high. Most significant 16 bits of Wake-Up Field D.
0x0
RW
Interrupt Enable Register
Address: 0x40002528, Reset: 0x0000, Name: T4IEN
Table 264. Bit Descriptions for T4IEN
Bits
Bit Name
Description
Reset
Access
[15:5]
RESERVED
Reserved.
0x0
R
4
ROLL
Rollover interrupt enable. Used only in free running mode. Set by user to generate an
interrupt when Timer 2 rolls over. Cleared by user to disable the rollover interrupt (default).
0x0
RW
3
WUFD
T4WUFD interrupt enable. Set by user code to generate an interrupt when T4VAL
reaches T4WUFD. Cleared by user code to disable T4WUFD interrupt (default).
0x0
RW
2
WUFC
T4WUFC interrupt enable. Set by user code to generate an interrupt when T4VAL
reaches T4WUFC. Cleared by user code to disable T4WUFC interrupt (default).
0x0
RW
1
WUFB
T4WUFB interrupt enable. Set by user code to generate an interrupt when T4VAL
reaches T4WUFB. Cleared by user code to disable T4WUFB interrupt (default).
0x0
RW
0
WUFA
T4WUFA interrupt enable. Set by user code to generate an interrupt when T4VAL
reaches T4WUFA. Cleared by user code to disable T4WUFA interrupt (default).
0x0
RW
