UG-549
ADuCM310 Hardware Reference Manual
Rev. C | Page 126 of 192
Master Status Register
Address: 0x40003404, Reset: 0x6000, Name: I2C1MSTA
Table 176. Bit Descriptions for I2C1MSTA
Bits
Bit Name
Description
Reset
Access
15
RESERVED
Reserved.
0x0
R
14
SCL_FILTERED
State of SCL line. This bit is the output of the glitch filter on SCL. SCL is
always pulled high when undriven.
0x1
R
13
SDA_FILTERED
State of SDA line. This bit is the output of the glitch-filter on SDA. SDA is
always pulled high when undriven.
0x1
R
12
MTXUFLOW
Master transmit underflow. MTXUFLOW asserts when the I
2
C master ends
the transaction due to a Tx FIFO empty condition. This bit is asserted only
when the IENMTX bit is set.
0x0
RC
11
MSTOP
Stop driven by this I
2
C master. MSTOP asserts when this I
2
C master drives
a stop condition on the I
2
C bus. This bit, when asserted, can indicate a
transaction completion, Tx underflow, Rx overflow, or a no acknowledge
by the slave. This is different from TCOMP because this bit is not asserted
when the stop condition occurs due to any other I
2
C master. No interrupt is
generated for the assertion of this bit. However, if IENCMP is 1, every stop
condition generates an interrupt and this bit can be read. When this bit is
read, it clears status.
0x0
RC
10
LINEBUSY
Line is busy. This bit asserts when a start is detected on the I
2
C bus. This bit
deasserts when a stop is detected on the I
2
C bus.
0x0
R
9
MRXOF
Master receive FIFO overflow. This bit asserts when a byte is written to the
receive FIFO when the FIFO is already full. When the bit is read, it clears the
status.
0x0
RC
8
TCOMP
Transaction complete or stop detected. This bit asserts when a stop condition
is detected on the I
2
C bus. If IENCMP is 1, an interrupt is generated when
this bit asserts. This bit only asserts if the master is enabled (MASEN = 1).
Use this bit to determine when it is safe to disable the master. It can also
wait for another master transaction to complete on the I
2
C bus when this
master loses arbitration. When this bit is read, it clears status. This bit can
drive an interrupt.
0x0
RC
7
NACKDATA
Acknowledge not received in response to data write. This bit asserts when
an acknowledge is not received in response to a data write transfer. If IENACK is
1, an interrupt is generated when this bit asserts. This bit can drive an interrupt.
This bit is cleared on a read of the I2C1MSTA register.
0x0
RC
6
MBUSY
Master busy. This bit indicates that the master state machine is servicing a
transaction. It is clear if the state machine is idle or if another device has
control of the I
2
C bus.
0x0
R
5
ALOST
Arbitration lost. This bit asserts if the master loses arbitration. If IENALOST
is 1, an interrupt is generated when this bit asserts. This bit is cleared on a
read of the I2C1MSTA register. This bit can drive an interrupt.
0x0
RC
4
NACKADDR
Acknowledge not received in response to an address. This bit asserts if an
acknowledge is not received in response to an address. If IENACK is 1, an
interrupt is generated when this bit asserts. This bit is cleared on a read of
the I2CMSTA register. This bit can drive an interrupt.
0x0
RC
3
MRXREQ
Master receive request. This bit asserts when there is data in the receive
FIFO. If IENMRX is 1, an interrupt is generated when this bit asserts. This bit
can drive an interrupt.
0x0
R
2
MTXREQ
Master transmit request. This bit asserts when the direction bit is 0 and the
transmit FIFO is either empty or not full. If IENMTX is 1, an interrupt is
generated when this bit asserts. This bit can drive an interrupt.
0x0
R
[1:0]
MTXFSTA
Master transmit FIFO status. These two bits show the master transmit FIFO
status and can be decoded as follows:
0x0
R
00 = FIFO empty.
10 = 1 byte in FIFO.
11 = FIFO full.
