UG-549
ADuCM310 Hardware Reference Manual
Rev. C | Page 144 of 192
REGISTER SUMMARY: SPI1
Table 205. SPI1 Register Summary
Address
Name
Description
Reset
Access
0x40030000
SPI1STA
Status register
0x0000
R
0x40030004
SPI1RX
Receive register
0x0000
R
0x40030008
SPI1TX
Transmit register
0x0000
W
0x4003000C
SPI1DIV
Baud rate selection register
0x0000
RW
0x40030010
SPI1CON
SPI configuration register
0x0000
RW
0x40030014
SPI1DMA
SPI DMA enable register
0x0000
RW
0x40030018
SPI1CNT
Transfer byte count register
0x0000
RW
REGISTER DETAILS: SPI1
Status Register
Address: 0x40030000, Reset: 0x0000, Name: SPI1STA
Table 206. Bit Descriptions for SPI1STA
Bits
Bit Name
Description
Reset
Access
15
RESERVED
Reserved.
0x0
R
14
CSRSG
Detected a rising edge on CS, in CONT mode. This bit causes an interrupt.
This can identify the end of an SPI data frame.
0x0
RC
0: cleared to 0 when the status register is read.
1: set to 1 when there was a rising edge in CS line, when the device was in
master mode, continuous transfer, high frequency mode, and CSIRQ_EN was
asserted.
13
CSFLG
Detected a falling edge on CS, in CONT mode. This bit causes an interrupt.
This can identify the start of an SPI data frame.
0x0
RC
0: cleared to 0 when the status register is read.
1: set to 1 when there was a falling edge in CS line, when the device was in
master mode, continuous transfer, high frequency mode, and CSIRQ_EN was
asserted.
12
CSERR
Detected a CS error condition.
0x0
RC
0: cleared to 0 when the status register is read.
1: set to 1 when the CS line was deasserted abruptly, even before the full
byte of data was transmitted completely. This bit causes an interrupt.
11
RXS
SPI Rx FIFO excess bytes present.
0x0
R
0: cleared to 0 when the number of bytes in the FIFO is less than or equal to
the number indicated in the MOD bits (SPI0CON[15:14]).
1: set to 1 when the number of bytes in the Rx FIFO is greater than the
number indicated in the MOD bits (SPI0CON[15:14]).
[10:8]
RXFSTA
SPI Rx FIFO status.
0x0
R
000: Rx FIFO empty.
001: 1 valid byte in the FIFO.
010: 2 valid bytes in the FIFO.
011: 3 valid bytes in the FIFO.
100: 4 valid bytes in the FIFO.
7
RXOF
SPI Rx FIFO overflow.
0x0
RC
0: cleared to 0 when the SPI1STA register is read.
1: set to 1 when the Rx FIFO was already full when new data was loaded to
the FIFO. This bit generates an interrupt, except when RFLUSH is set in
SPI1CON.
6
RX
SPI Rx IRQ. Not available in DMA mode. Set when a receive interrupt occurs.
0x0
RC
0: cleared to 0 when the SPI1STA register is read.
1: set to 1 when TIM in SPI1CON is cleared and the required number of bytes
have been received.
