UG-549
ADuCM310 Hardware Reference Manual
Rev. C | Page 156 of 192
Bits
Bit Name
Description
Reset
Access
2
TERI
Trailing edge RI. If set, this bit self clears after COMMSR is read.
0x0
R
0: RI has not changed from 0 to 1 since COMMSR was last read.
1: RI changed from 0 to 1 since COMMSR was last read.
1
DDSR
Delta DSR. If set, this bit self clears after COMMSR is read.
0x0
R
0: DSR has not changed state since COMMSR was last read.
1: DSR changed state since COMMSR was last read.
0
DCTS
Delta CTS. If set, this bit self clears after COMMSR is read.
0x0
R
0: CTS has not changed state since COMMSR was last read.
1: CTS changed state since COMMSR was last read.
Scratch Buffer Register
Address: 0x4000501C, Reset: 0x0000, Name: COMSCR
Table 222. Bit Descriptions for COMSCR
Bits
Bit Name
Description
Reset
Access
[15:8]
RESERVED
Reserved.
0x0
R
[7:0]
SCR
Scratch. The scratch register is an 8-bit register stores intermediate results.
The value contained in the scratch register does not affect UART functionality
or performance. Only 8 bits of this register are implemented. Bits[15:8] are
read only and always return 0x00 when read. SCR is writable with any value
from 0 to 255. A read returns the last value written.
0x0
RW
Fractional Baud Rate Register
Address: 0x40005024, Reset: 0x0000, Name: COMFBR
Table 223. Bit Descriptions for COMFBR
Bits
Bit Name
Description
Reset
Access
15
FBEN
Fractional baud rate generator enable. The generating of fractional baud
rate can be described by the following formula and the final baud rate of
UART operation is calculated as
Baud Rate
= (
UCLK
/
CDPCLK
/(2 × (
M
+
N
/2048)) 16 ×
COMDIV
0x0
RW
[14:13]
RESERVED
Reserved.
0x0
R
[12:11]
DIVM
Fractional baud rate M divide Bit 1 to Bit 3. These bits must not be 0.
0x0
RW
[10:0]
DIVN
Fractional baud rate N divide Bit 0 to Bit 2047.
0x0
RW
Baud Rate Divider Register
Address: 0x40005028, Reset: 0x0001, Name: COMDIV
Table 224. Bit Descriptions for COMDIV
Bits
Bit Name
Description
Reset
Access
[15:0]
DIV
Baud rate divider. The COMDIV register must not be 0, which is not specified.
The range of allowed DIV values is from 1 to 65,535.
0x1
RW
