ADuCM310 Hardware Reference Manual
UG-549
Rev. C | Page 17 of 192
ARM CORTEX-M3 PROCESSOR
ARM CORTEX-M3 PROCESSOR FEATURES
High Performance
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1.25 DMIPS/MHz.
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Many instructions, including multiply, are single cycle.
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Separate data and instruction buses allow simultaneous data and instruction accesses to be performed.
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Optimized for single-cycle flash usage.
Low Power
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Low standby current.
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Core implemented using advanced clock gating so that only the actively used logic consumes dynamic power.
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Power-saving mode support (sleep and deep sleep modes). The design has separate clocks to allow unused parts of the processor to
be stopped.
Advanced Interrupt Handling
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The nested vectored interrupt controller (NVIC) supports up to 240 interrupts, of which the
supports 50. The vectored
interrupt feature greatly reduces interrupt latency because there is no need for software to determine which interrupt handler to
serve. In addition, there is no need to have software to set up nested interrupt support.
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The ARM Cortex-M3 processor automatically pushes registers onto the stack at the entry interrupt and retrieves them at the exit
interrupt. This reduces interrupt handling latency and allows interrupt handlers to be normal C functions.
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Dynamic priority control for each interrupt.
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Latency reduction using late arrival interrupt acceptance and tail-chain interrupt entry.
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Immediate execution of a nonmaskable interrupt request for safety-critical applications.
System Features
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Support for bit-band operation and unaligned data access.
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Advanced fault handling features include various exception types and fault status registers.
Debug Support
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Serial wire debug interfaces (SW-DP).
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Flash patch and breakpoint (FPB) unit for implementing breakpoints. Limited to two hardware breakpoints.
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Data watchpoint and trigger (DWT) unit for implementing watchpoints trigger resources and system profiling. Limited to one
hardware watchpoint. The DWT does not support data matching for watchpoint generation because it only has one comparator.
