ADuCM310 Hardware Reference Manual
UG-549
Rev. C | Page 175 of 192
Control Register
Address: 0x40002508, Reset: 0x0040, Name: T4CON
Table 256. Bit Descriptions for T4CON
Bits
Bit Name
Description
Reset
Access
[15:12]
RESERVED
Reserved.
0x0
R
11
STOP_WUFA
Disables updating Field A register T4WUFA. When set, this bit stops the
Wake-Up Field A register T4WUFA from being updated with the interval
register I2INC value. This allows the user to update the interval T4INC or
T4WUFA registers safely.
0x0
RW
[10:9]
CLK
Clock select.
0x0
RW
00: PCLK: peripheral clock (default).
01: LFOSC: 32 kHz internal oscillator.
10: LFOSC: 32kHz internal oscillator.
11: ECLKIN: external clock from P1.0.
8
WUEN
Wake-up enable.
0x0
RW
0: DIS: Cleared by user to disable the wake-up timer when the core clock is off.
1: EN: Set by user to enable the wake-up timer even when the core clock is off.
7
ENABLE
Timer enable.
0x0
RW
0: DIS: Disable the timer (default).
1: EN: Enable the timer.
6
MOD
Timer mode.
0x1
RW
0: PERIODIC: Cleared by user to operate in periodic mode. In this mode, the
timer counts up to T4WUFD.
1: FREERUN: Set by user to operate in free running mode (default).
[5:4]
RESERVED
Reserved. Write these bits 0.
0x0
RW
3
FREEZE
Freeze enable.
0x0
RW
0: DIS: Cleared by user to disable this feature (default).
1: EN: Set by user to enable the freeze of the high 16 bits after the lower
bits have been read from T4VAL0. This ensures that the software reads an
atomic shot of the timer. T4VAL1 unfreezes after it has been read.
2
RESERVED
Reserved.
0x0
RW
[1:0]
PRE
Prescaler.
0x0
RW
00: PREDIV1: Source Clock/1 (default). If the selected clock source is PCLK,
this setting results in a prescaler of 4.
01: PREDIV16: Source Clock/16.
10: PREDIV256: Source Clock/256.
11: PREDIV32768: Source Clock/32,768.
12-Bit Interval for Wake-Up Field A Register
Address: 0x4000250C, Reset: 0x00C8, Name: T4INC
Table 257. Bit Descriptions for T4INC
Bits
Bit Name
Description
Reset
Access
[15:12]
RESERVED
Reserved
0x0
R
[11:0]
INTERVAL
Interval for Wake-Up Field A
0x0C8
RW
Wake-Up Field B—Least Significant 16 Bits Register
Address: 0x40002510, Reset: 0x1FFF, Name: T4WUFB0
Table 258. Bit Descriptions for T4WUFB0
Bits
Bit Name
Description
Reset
Access
[15:0]
T4WUFBL
Wake-Up Field B low. Least significant 16 bits of Wake-Up Field B.
0x1FFF
RW
