ADuCM310 Hardware Reference Manual
UG-549
Rev. C | Page 95 of 192
Flash 0 ECC Error Address Register
Address: 0x40018074, Reset: 0x00000000, Name: FEEECCADDR0
Table 122. Bit Descriptions for FEEECCADDR0
Bits
Bit Name
Description
Reset
Access
[31:19]
RESERVED
Reserved.
0x0
R
[18:0]
VALUE
This register has the address of Flash 0 for which the ECC error is detected.
0x0
R
Flash 1 ECC Error Address Register
Address: 0x40018078, Reset: 0x00000000, Name: FEEECCADDR1
Table 123. Bit Descriptions for FEEECCADDR1
Bits
Bit Name
Description
Reset
Access
[31:19]
RESERVED
Reserved.
0x0
R
[18:0]
VALUE
This register has the address of Flash 1 for which ECC error is detected.
0x0
R
Cache Status Register
Address: 0x400180C0, Reset: 0x00000002, Name: CACHESTAT
Table 124. Bit Descriptions for CACHESTAT
Bits
Bit Name
Description
Reset
Access
[31:20]
RESERVED
Reserved.
0x0
R
18
DLOCK
This bit is set when the data cache is locked and cleared when the data
cache is unlocked.
0x0
R
17
DEN
If this bit is set, the data cache is enabled and when cleared, the data cache
is disabled. This bit is also cleared when CACHESTAT[16] is set.
0x0
R
16
DINIT
This bit is set when the data cache memory initialization starts and clears
when initialization is done. The data cache is disabled when this bit is set.
0x0
R
[15:4]
RESERVED
Reserved.
0x0
R
2
ILOCK
This bit is set when the instruction cache is locked and cleared when the
instruction cache is unlocked.
0x0
R
1
IEN
If this bit is set, the instruction cache is enabled and when cleared, the
instruction cache is disabled. This bit is also cleared when CACHESTAT[0] is set.
0x1
R
0
IINIT
This bit is set when the instruction cache memory initialization starts and
clears when initialization is done. The instruction cache is disabled when
this bit is set.
0x0
R
