UG-549
ADuCM310 Hardware Reference Manual
Rev. C | Page 112 of 192
I
2
C Clock Control
The I
2
C peripherals are clocked by a gated 20 MHz system clock (PCLK). The CLKCON5[3] bit must be cleared to enable the clock to the
I
2
C0 block. Similarly, the CLKCON5[4] bit must be cleared to enable the clock to the I
2
C1 block. CLKCON1[10:8] allow the I
2
C block to
be clocked with a slower clock by allowing the 20 MHz clock to be divided, which helps to reduce power.
The I
2
C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz)
or in standard mode (100 kHz).
The bit rate is defined in the I2CxDIV MMR as follows:
f
SCL
=
f
I2CCLK
/(
LOW
+
HIGH
+ 3)
where:
f
I2CCLK
=
f
PCLK
/
I2CCD
.
f
PCLK
is the system clock, 20 MHz.
I2CCD
is the clock divide value and is set by the CLKCON1[10:8].
HIGH
is the high period of the clock, I2CxDIV[15:8] = (REQD_HIGH_TIME/UCLK_PERIOD) − 2.
LOW
is the low period of the clock, I2CxDIV[7:0] = (REQD_LOW_TIME/UCLK_PERIOD) − 1.
For 100 kHz SCL operation, with a low time of 5 µs and a high time of 5 µs, and a UCLK frequency of 20 MHz,
HIGH
= (5 µs /(1/20,000,000)) − 2 = 98 = 0x62
LOW
= (5 µs /(1/20,000,000)) − 1 = 99 = 0x63
f
SCL
= 20,000,000/(98 + 99 + 3) = 100 kHz
I
2
C OPERATING MODES
Master Transfer Initiation
If the master enable bit (I2CxMCON[0], MASEN) is set, a master transfer sequence is initiated by writing a value to the I2CxADRx register.
If there is valid data in the I2CxMTX register, it is the first byte transferred in the sequence after the address byte during a write sequence.
Slave Transfer Initiation
If the slave enable bit (I2CxSCON[0], SLVEN) is set, a slave transfer sequence is monitored for the device address in Register I2CxID0,
Register I2CxID1, Register I2CxID2, or Register I2CxID3. If the device address is recognized, the device participates in the slave transfer
sequence.
Note that a slave operation always starts with the assertion of one of three interrupt sources: read request (MRXREQ, SRXREQ), write
request (MTXREQ, STXREQ), or general call (GCINT) interrupt. The software must always look for a stop interrupt to ensure that the
transaction has completed correctly and to deassert the stop interrupt status bit.
Rx/Tx Data FIFOs
The transmit data path consists of a master and slave Tx FIFO, I2CxMTX and I2CxSTX (each two bytes deep), and a transmit shifter. The
transmit status bits in I2CxMSTA[1:0] and I2CxSSTA[0] denote whether there is valid data in the Tx FIFO. Data from the Tx FIFO is loaded
into the Tx shifter when a serial byte begins transmission. If the Tx FIFO is not full during an active transfer sequence, the transmit
request bit (I2CxMSTA[2] or I2CxSSTA[2]) asserts.
Figure 23 shows the effect of not having the slave Tx FIFO full at the start of a read request from a master. An extra transmit interrupt
may be generated after the read bit. This extra transmit interrupt occurs if the Tx FIFO is not full.
RE
AD
DEVICE
ADDRESS
SDA LINE
ACK
NO
ACK
ACK
ACK
ACK
S
TOP
R/
W
DATA (n + 2)
DATA (n + x)
DATA (n + 1)
DATA (n)
TRANSMIT
INTERRUPT
TRANSMIT
INTERRUPT
EXTRA TRANSMIT INTERRUPT
POSSIBLE IF FIFO LOADED IN
PREVIOUS INTERRUPT
TRANSMIT
INTERRUPT
TRANSMIT
INTERRUPT
TRANSMIT
INTERRUPT
1
1461-
021
Figure 23. I
2
C Slave Tx Interrupt Details
