ADuCM310 Hardware Reference Manual
UG-549
Rev. C | Page 177 of 192
Status Register
Address: 0x4000252C, Reset: 0x0000, Name: T4STA
Table 265. Bit Descriptions for T4STA
Bits
Bit Name
Description
Reset
Access
[15:9]
RESERVED
Reserved.
0x0
R
8
PDOK
Enable bit synchronized. Indicates when a change in the enable bit is
synchronized to the 32 kHz clock domain. It is set high when the enable bit
(Bit 5) in the control register is set or cleared. It returns low when the change in
the enable bit has been synchronized to the 32 kHz clock domain.
0x0
R
7
FREEZE
Timer value freeze. Set automatically to indicate that the value in T4VAL1 is
frozen. Cleared by automatically when T4VAL1 is read.
0x0
R
6
IRQCRY
Wake-up status to power down. Set automatically when any of the interrupts are
still set in the external crystal clock domain. Cleared automatically when the
interrupts are cleared, allowing power-down mode. User code must wait for this
bit to be cleared before entering power-down mode.
0x0
R
5
RESERVED
Reserved.
0x0
R
4
ROLL
Rollover interrupt flag. Used only in free running mode. Set automatically to indicate
a rollover interrupt has occurred. Cleared automatically after a write to T4CLRI.
0x0
R
3
WUFD
T4WUFD interrupt flag. Set automatically to indicate a comparator interrupt has
occurred. Cleared automatically after a write to the corresponding bit in T4CLRI.
0x0
R
2
WUFC
T4WUFC interrupt flag. Set automatically to indicate a comparator interrupt has
occurred. Cleared automatically after a write to the corresponding bit in T4CLRI.
0x0
R
1
WUFB
T4WUFB interrupt flag. Set automatically to indicate a comparator interrupt has
occurred. Cleared automatically after a write to the corresponding bit in T4CLRI.
0x0
R
0
WUFA
T4WUFA interrupt flag. Set automatically to indicate a comparator interrupt has
occurred. Cleared automatically after a write to the corresponding bit in T4CLRI.
0x0
R
Clear Interrupt Register
Address: 0x40002530, Reset: 0x0000, Name: T4CLRI
Table 266. Bit Descriptions for T4CLRI
Bits
Bit Name
Description
Reset
Access
[15:5]
RESERVED
Reserved.
0x0
R
4
ROLL
Rollover interrupt clear. Used only in free running mode. Set by user code to
clear a rollover interrupt flag. Cleared automatically after synchronization.
0x0
RW
3
WUFD
T4WUFD interrupt clear.
0x0
RW
2
WUFC
T4WUFC interrupt clear. Set by user code to clear a T4WUFC interrupt flag.
Cleared automatically after synchronization.
0x0
RW
1
WUFB
T4WUFB interrupt clear. Set by user code to clear a T4WUFB interrupt flag.
Cleared automatically after synchronization.
0x0
RW
0
WUFA
T4WUFA interrupt clear. Set by user code to clear a T4WUFA interrupt flag.
Cleared automatically after synchronization.
0x0
RW
Wake-Up Field A—Least Significant 16 Bits Register
Address: 0x4000253C, Reset: 0x1900, Name: T4WUFA0
Table 267. Bit Descriptions for T4WUFA0
Bits
Bit Name
Description
Reset
Access
[15:0]
T4WUFAL
Wake-Up Field A low. Least significant 16 bits of Wake-Up Field A.
0x1900
RW
Wake-Up Field A—Most Significant 16 Bits Register
Address: 0x40002540, Reset: 0x0000, Name: T4WUFA1
Table 268. Bit Descriptions for T4WUFA1
Bits
Bit Name
Description
Reset
Access
[15:0]
T4WUFAH
Wake-Up Field A high. Most significant 16 bits of Wake-Up Field A.
0x0
RW
