Analog Devices ADuCM310, Hardware Reference Manual

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ADuCM310 Hardware Reference Manual UG-549
Rev. C | Page 57 of 192
Position Number Vector Wake Up Processor from Mode 1 Wake Up Processor from Mode 2 or Mode 3
20 SPI1 Yes No
21 I
2
C0 slave Yes No
22 I 2 C0 master Yes No
23 PLA 0 Yes No
24 PLA 1 Yes No
25 DMA error Yes No
26 DMA Channel 0 (SPI0 Tx) done Yes No
27 DMA Channel 1 (SPI0 Rx) done Yes No
28 DMA Channel 2 (SPI1 Tx) done Yes No
29 DMA Channel 3 (SPI1 Rx) done Yes No
30 DMA Channel 4 (UART Tx) done Yes No
31 DMA Channel 5 (UART Rx) done Yes No
32 DMA Channel 6 (I
2
C0 slave Tx)
done
Yes No
33 DMA Channel 7 (I
2
C0 slave Rx)
done
Yes No
34 DMA Channel 8 (I
2
C0 master)
done
Yes No
35 DMA Channel 9 (I
2
C1 slave Tx)
done
Yes No
36 DMA Channel 10 (I 2 C1 slave Rx)
done
Yes No
37 DMA Channel 11 (I
2
C1 master)
done
Yes No
38 DMA Channel 12 (ADC) done Yes No
39 DMA Channel 13 (Flash) done Yes No
40 Reserved
41 Reserved
42 Reserved
43 Reserved
44 I
2
C1 slave Yes No
45 I 2 C1 master Yes No
46 PLA 2 Yes No
47 PLA 3 Yes No
48 GP Timer 2 Yes No
49 Low Voltage Die Interrupt 1 Yes No
50 PWM trip Yes No
51 PWM PAIR0 Yes No
52 PWM PAIR1 Yes No
53 PWM PAIR2 Yes No
54 PWM PAIR3 Yes No
Internally to the ARM Cortex-M3 processor, the highest user-programmable priority (0) is treated as fourth priority—after a reset, an NMI,
and a hard fault. The
ADuCM310 implements three priority bits, which means that eight priority levels are available as programmable
priorities. Note that 0 is the default priority for all the programmable priorities. If the same priority level is assigned to two or more
interrupts, their hardware priority (the lower the position number) determines the order in which the processor activates them. For
example, if both SPI0 and SPI1 are Priority Level 1, then SPI0 has higher priority.
To enable an interrupt for any peripheral listed from 0 to 31 in Table 63, set the appropriate bit in the ISER0 register; ISER0 is a 32-bit
register and each bit corresponds to the first 32 entries in Table 63.
For example, to enable External Interrupt 3, the interrupt source in the NVIC, set ISER0[4] = 1. Similarly, to disable External Interrupt 3,
set ICER0[4] = 1.
To enable an interrupt for any peripheral listed from 32 to 54 in Table 63, set the appropriate bit in the ISER1 register; ISER1 is a 32-bit
register and ISER1 Bit 0 to Bit 21 correspond to the entries 32 to 54 in Table 63.