Analog Devices ADuCM310, Hardware Reference Manual

Page: 56 / 192

UG-549 ADuCM310 Hardware Reference Manual
Rev. C | Page 56 of 192
SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS
CORTEX-M3 AND FAULT MANAGEMENT
The ADuCM310 integrates an ARM Cortex-M3 processor, which supports a number of system exceptions and interrupts generated by
peripherals. Table 62 lists the ARM Cortex-M3 processor system exceptions.
Table 62. System Exceptions
Number Type Priority Description
1 Reset −3 (highest) Any reset.
2 NMI −2 Nonmaskable not connected on ADuCM310 .
3 Hard fault −1 All fault conditions if the corresponding fault handler is not enabled.
4 Memory management fault Programmable Memory management fault; access to illegal locations.
5 Bus fault Programmable Prefetch fault, memory access fault, data abort, and other address/memory
related faults.
6 Usage fault Programmable Same as undefined instruction executed or illegal state transition attempt.
7 to 10 Reserved Not applicable Reserved.
11 SVCall Programmable System service call with SVC instruction. Used for system function calls.
12 Debug monitor Programmable Debug monitor (breakpoint, watchpoint, or external debug requests).
13 Reserved Not applicable Reserved.
14 PendSV Programmable Pendable request for system service. Used for queuing system calls until other
tasks and interrupts are serviced.
15 SYSTICK Programmable System tick timer.
The peripheral interrupts are controlled by the NVIC and are listed in Table 63. All interrupt sources can wake up the device from Mode 1.
Only a limited number of interrupts can wake up the processor from the low power modes (Mode 2 or Mode 3), as shown in Table 63.
When the device is woken up from Mode 2 or Mode 3, it returns to Mode 0. If the processor enters any power mode from Mode 1 to
Mode 3 while the processor is in an interrupt handler, only an interrupt source with a higher priority than the current interrupt can wake
up the device (higher value in IPRx registers).
Two steps are normally required to configure an interrupt:
•
Configuring a peripheral to generate an interrupt request to the NVIC.
•
Configuring the NVIC for that peripheral request.
Table 63. Interrupt Vector Table
Position Number Vector Wake Up Processor from Mode 1 Wake Up Processor from Mode 2 or Mode 3
0 Wake-up timer Yes Yes
1 External Interrupt 0 Yes Yes
2 External Interrupt 1 Yes Yes
3 External Interrupt 2 Yes Yes
4 External Interrupt 3 Yes Yes
5 External Interrupt 4 Yes Yes
6 External Interrupt 5 Yes Yes
7 External Interrupt 6 Yes Yes
8 External Interrupt 7 Yes Yes
9 External Interrupt 8 Yes Yes
10 Watchdog timer Yes Yes
11 Reserved
12 Reserved
13 Low Voltage Die Interrupt 0 Yes No
14 Reserved
15 GP Timer 0 Yes No
16 GP Timer 1 Yes No
17 Flash controller Yes No
18 UART Yes No
19 SPI0 Yes No