Analog Devices ADuCM310 Hardware Reference Manual Download Page 41

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ADuCM310 Hardware Reference Manual

UG-549

Rev. C | Page 41 of 192

IDAC1 Data Register

Address: 0x40086808, Reset: 0x00000000, Name: IDAC1DAT

Table 30. Bit Descriptions for IDAC1DAT

Bits

Bit Name

Description

Reset

Access

[31:28]

RESERVED

Reserved. Write 0.

0x0

[27:17]

DATH

IDAC1 high data.

0x0

[16:12]

DATL

IDAC1 low data.

0x0

[11:6]

RESERVED

Reserved.

0x0

[5:0]

SYNC

IDAC1 synchronization bits. These six bits are common to the six IDACs.

Each bit set to 1 prevents the corresponding channel from updating
immediately. The channel updates when the bit changes to 0.

0x00

IDAC1 Control Register

Address: 0x4008680C, Reset: 0x01, Name: IDAC1CON

Table 31. Bit Descriptions for IDAC1CON

Bits

Bit Name

Description

Reset

Access

CLRB

IDAC1 clear bit.

0x0

0: clear IDAC1DAT.

1: enable write.

SHT_EN

IDAC1 shutdown enable. Enables automatic shutdown in case of
overtemperature.

0x0

0: disable this function.

1: enable this function.

[5:2]

IDAC1 bandwidth. See the IDAC Output Filter section for more details.

0x0

PUL

IDAC1 pull down.

0x0

0: disable the pull-down current source.

1: enable the pull-down current source.

IDAC1 power down.

0x1

0: powers up IDAC1.

1: powers down IDAC1.

IDAC2 Data Register

Address: 0x40086810, Reset: 0x00000000, Name: IDAC2DAT

Table 32. Bit Descriptions for IDAC2DAT

Bits

Bit Name

Description

Reset

Access

[31:28]

RESERVED

Reserved. Write 0.

0x0

[27:17]

DATH

IDAC2 high data.

0x0

[16:12]

DATL

IDAC2 low data.

0x0

[11:6]

RESERVED

Reserved.

0x0

[5:0]

SYNC

IDAC2 synchronization bits. These six bits are common to the six IDACs.

Each bit set to 1 prevents the corresponding channel from updating
immediately. The channel updates when the bit changes to 0.

0x00

Summary of Contents for ADuCM310

Page 1: ...data sheet which must be consulted in conjunction with this reference manual when using the device FUNCTIONAL BLOCK DIAGRAM ON CHIP 1 8V LDO MEMORY 256k FLASH 32k SRAM ARM CORTEX M3 PROCESSOR MUX RES...

Page 2: ...ram 19 ADC Circuit Overview 19 ADC Circuit Operation 20 ADC Transfer Function 20 ADC Typical Setup Sequence 22 ADC Input Buffer 22 ADC Internal Channels 23 ADC Support Circuits 24 Register Summary ADC...

Page 3: ...8 SPI and Power Down Modes 139 Register Summary SPI0 140 Register Details SPI0 140 Register Summary SPI1 144 Register Details SPI1 144 UART Serial Interface 148 UART Features 148 UART Overview 148 UAR...

Page 4: ...Deleted Endnote 1 Table 74 Renumbered Sequentially 64 Changes to Protection Integrity Section 78 Added ECC Error Handling Section 81 Added ECC Error During Read Section and ECC Error During Execution...

Page 5: ...ite access RC Memory location is cleared after reading it R Memory location is read access only A read always returns 0 unless otherwise specified W Memory location is write access only MMR bits that...

Page 6: ...are 12 bit string DACs with output buffers capable of sourcing between 10 mA and 50 mA and all are capable of driving 10 nF capacitive loads The low drift current DACs have 14 bit resolution and have...

Page 7: ...Cs 2 byte transmit and receive FIFOs for the master and slave Support for DMA Automatic clock stretching option Two SPIs Master or slave mode with separate 4 byte Rx and Tx FIFOs Rx and Tx DMA channe...

Page 8: ...a and in circuit download VENDOR SPECIFIC PRIVATE PERIPHERAL BUS EXTERNAL PRIVATE PERIPHERAL BUS INTERNAL EXTERNAL DEVICE 1GB NOT AVAILABLE IN ADuCM310 EXTERNAL RAM 1GB NOT AVAILABLE IN ADuCM310 PERIP...

Page 9: ...External clock input ECLKIN is available via the GPIO pin CLOCKING ARCHITECTURE BLOCK DIAGRAM HFOSC 16MHz OSC WATCHDOG TIMER WAKE UP TIMER TIMER0CLK 01 11 00 01 11 00 10 T4CON 9 10 CLKCON0 1 0 TIMER1C...

Page 10: ...d to change from the internal 16 MHz oscillator to the external HFXTAL observe the following procedure 1 Check that HFXTAL is stable by reading CLKSTAT0 14 12 2 Change the system clock to the internal...

Page 11: ...ble 6 Bit Descriptions for CLKCON1 Bits Bit Name Description Reset Access 15 11 RESERVED Reserved 0x0 R 10 8 CDPCLK PCLK divide bits 0x2 RW 000 Reserved 001 Reserved 010 DIV4 Divide by 4 PCLK is a qua...

Page 12: ...LK I2 C1 clock It controls the gate on UCLK I2 C1 in Power Mode 0 and Power Mode 1 In Power Mode 2 and Power Mode 3 the I2 C1 UCLK is always off and this bit has no effect 0x0 RW 0 clock on 1 clock of...

Page 13: ...OCK System PLL unlock This bit is sticky SPLLUNLOCK is set when the PLL loses its lock SPLLUNLOCK is used as the interrupt source to signal the core that a lock was lost Writing a 1 to this bit clears...

Page 14: ...rocessor into sleep mode it is independent of the power mode settings of the PMU When the ADuCM310 wakes up from any of the low power modes the device returns to Mode 0 Power Mode CORE_SLEEP Mode Mode...

Page 15: ...CON 0 Power off the ADC pADI_IDAC0 IDACCON 0x1 Turn off IDAC0 pADI_IDAC1 IDACCON 0x1 Turn off IDAC1 pADI_IDAC2 IDACCON 0x1 Turn off IDAC2 pADI_IDAC3 IDACCON 0x1 Turn off IDAC3 pADI_VDAC0 DACCON 0x100...

Page 16: ...hese bits contain the last power mode value entered by user code Note that to place the Cortex in SLEEPDEEP mode for hibernate the Cortex M3 system control register Register 0xE000ED10 must be configu...

Page 17: ...o serve In addition there is no need to have software to set up nested interrupt support The ARM Cortex M3 processor automatically pushes registers onto the stack at the entry interrupt and retrieves...

Page 18: ...interrupt support Vectored interrupt support Dynamic priority changes support Interrupt masking In addition the NVIC has a nonmaskable interrupt NMI input The NVIC is implemented on the ADuCM310 and m...

Page 19: ...register for its conversion result For example when AIN0 is selected the result appears in ADCDAT0 if AIN7 is selected the result appears in ADCDAT7 For a differential measurement the result always a...

Page 20: ...ctly to the inputs to fully charge the capacitor arrays and eliminate any precharge buffer errors The timing for the acquisition phase is set by ADCCNVC 25 16 set this value to 1 s for ADC update rate...

Page 21: ...he average of the two signals AIN AIN 2 and is therefore the voltage that the two inputs are centered on This results in the span of each input being CM VREF 2 This voltage must be set up externally a...

Page 22: ...o 1 before starting another sequence and reconfiguring the ADC back to continuous conversion mode This ensures that the sequencer restarts with the first selected channel in ADCSEQ ADC INPUT BUFFER MU...

Page 23: ...f the temperature of the ADuCM310 low voltage analog die An ADC temperature sensor conversion differs from a standard ADC voltage The ADC performance specifications do not apply to the temperature sen...

Page 24: ...resolution Therefore if the 2 505V internal reference is used the LSB resolution of ADCDAT is 38 225 V In this case the ADCOF LSB resolution is 9 556 V When performing an offset calibration apply 0 V...

Page 25: ...ote that when using the sequencer and the input buffer are enabled with chop mode enabled ensure that an odd number of channels are enabled in the sequence for example 5 7 or 9 Two consecutive sequenc...

Page 26: ...reference source It is also possible to select an external reference source through the ADC_CAPP pin To select an external voltage source as the ADC reference source ensure the following ADCCON 7 0 to...

Page 27: ...ndefined R 0x4008602C ADCDAT11 ADC11 data and flags Undefined R 0x40086030 ADCDAT12 ADC12 data and flags Undefined R 0x40086040 ADCDAT16 ADC16 data and flags Undefined R 0x40086044 ADCDAT17 ADC17 data...

Page 28: ...0 clear to 0 to disable ADC DMA access 1 set to 1 to enable ADC DMA access 2 0 C_TYPE ADC conversion type 0x0 RW 00 no conversion idle mode 01 DIO pin starts conversion P2 4 10 single conversion 11 c...

Page 29: ...AIN8 0x09 AIN9 0x0A to 0x0F reserved 0x10 VREFP_NADC connect ADC_REFP to negative input 0x11 VREFN_NADC connect ADC_REFN to negative input use this setting for single ended measurements 0x12 AGND 0x13...

Page 30: ...led channel after the second sequence for the final result ADC Sequencer Stall Status Register Address 0x40086084 Reset 0x00000001 Name ADCSEQS Table 17 Bit Descriptions for ADCSEQS Bits Bit Name Desc...

Page 31: ...IR Select comparator direction 0x0 RW 0 ADCTH less than Channel 4 data 1 ADCTH larger than Channel 4 data 0 EN Digital comparator enable 0x0 RW 0 disable 1 enable ADC Conversion Configuration Register...

Page 32: ...bits for manual control of input buffer chop switches 0x0 RW 00 P N input buffers offset polarity is 01 P N input buffers offset polarity is 10 P N input buffers offset polarity is 11 P N input buffer...

Page 33: ...e Output Driving Buffer A 5 4 RESERVED Reserved 0x0 RW 3 AFE_REF_EXT Select reference source for buffered reference outputs 0x0 RW 0 select internal 2 5 V reference 1 select external 2 5 V reference 2...

Page 34: ...Figure 9 Example IDAC Circuit IDAC3 IDAC OVERVIEW Precision Current Generation and Fault Protection The reference current for the IDACs is generated by a precision internal band gap voltage reference...

Page 35: ...die HVCON 11 controls the SOA shutdown clamping voltage The SOA clamping voltage is controlled in two ways When HVCON 11 0 the default negative shutdown voltage is clamped at approximately 1 75 V Whe...

Page 36: ...C Reference Resistor Error Shutdown The IREF pin is connected to ground via a 3 16 k resistor to generate a reference current for the IDACs The value of this resistor directly affects the output curre...

Page 37: ...4 6 16 Next 4 bits correction array IDACCOR_TypeDef define pIDACCOR IDACCOR_TypeDef 0x40980 The correction factor is the value that must be added or subtracted from the ideal value for the IDACxDAT re...

Page 38: ...31 iSh 0 if iIdealVal iSh psIDAC iChan IDACDAT iIdealVal iSh 0x3FF8 14 iError 12 Output corrected value else psIDAC iChan IDACDAT 0 iError 12 Output corrected value return 1 int IdacCor int iChan int...

Page 39: ...current source HVCON 1 0 switch on the SOA sink current on the high voltage die Ensure that HVCON 11 0 to avoid a negative voltage undershoot when the shutdown is enabled Set up the IDAC3CON register...

Page 40: ...R DETAILS IDAC IDAC0 Data Register Address 0x40086800 Reset 0x00000000 Name IDAC0DAT Table 28 Bit Descriptions for IDAC0DAT Bits Bit Name Description Reset Access 31 28 RESERVED Reserved Write 0 0x0 R...

Page 41: ...x0 RW 0 clear IDAC1DAT 1 enable write 6 SHT_EN IDAC1 shutdown enable Enables automatic shutdown in case of overtemperature 0x0 RW 0 disable this function 1 enable this function 5 2 BW IDAC1 bandwidth...

Page 42: ...it Name Description Reset Access 31 28 RESERVED Reserved Write 0 0x0 R 27 17 DATH IDAC3 high data 0x0 RW 16 12 DATL IDAC3 low data 0x0 RW 11 6 RESERVED Reserved 0x0 R 5 0 SYNC IDAC3 synchronization bi...

Page 43: ...0 clear IDAC1DAT 1 enable write 6 SHT_EN IDAC4 shutdown enable Enables automatic shutdown in case of overtemperature 0x0 RW 0 disable this function 1 enable this function 5 2 BW IDAC4 bandwidth See t...

Page 44: ...able the pull down current source 1 enable the pull down current source 0 PD IDAC5 power down 0x1 RW 0 powers up IDAC5 1 powers down IDAC5 IDAC6 Data Register Address 0x40086830 Reset 0x00000000 Name...

Page 45: ...rimmed negative pull down voltage on SOA is disabled When 0 the lowest voltage is 1 75 V Default is 0x0 meaning pull down voltage is approximately 1 75 V 10 9 OTI_TRIM These bits control the high volt...

Page 46: ...are capable of driving a 10 nF load VDAC0 VDAC1 0 V to 3 V full scale output specified to drive a 75 load 40 mA maximum Only the low voltage die is required These VDACs can select from two reference s...

Page 47: ...e feedback circuitry on the output buffer shown in Figure 1 and Figure 2 When DACxCON 10 9 11 the output voltage range is smaller See the ADuCM310 data sheet specifications for more details on the out...

Page 48: ...s the difference between VDACVDD and the maximum allowed output voltage on VDAC7 LOAD ON VDAC7 HEADROOM VDACV DD VDAC7 MAXIMUM OUTPUT VOLTAGE mV 700 600 500 400 300 200 100 0 100 200 300 500 1000 HEAD...

Page 49: ...DAT DAC4 data register 0x00000000 RW 0x40086418 DAC5DAT DAC5 data register 0x00000000 RW 0x4008641C DAC6DAT DAC6 data register 0x00000000 RW 0x40086420 DAC7DAT DAC7 data register 0x00000000 RW REGISTE...

Page 50: ...SERVED Reserved 0x0 RW 1 0 DAC1_RN DAC1 reference selection These bits set the DAC range A write to these bits has immediate effect on the DAC 0x0 RW 00 internal reference 01 reserved 10 reserved 11 A...

Page 51: ...ternal reference 01 reserved 10 reserved 11 AVDD AGND DAC4 Control Register Address 0x40082410 Reset 0x0100 Name DAC4CON Table 50 Bit Descriptions for DAC4CON Bits Bit Name Description Reset Access 15...

Page 52: ...SERVED Reserved 0x0 RW 1 0 DAC5_RN DAC5 reference selection These bits set the DAC range A write to these bits has immediate effect on the DAC 0x0 RW 00 internal reference 01 reserved 10 reserved 11 A...

Page 53: ...RW 00 internal reference 01 reserved 10 reserved 11 AVDD AGND DAC0 Data Register Address 0x40086404 Reset 0x00000000 Name DAC0DAT Table 54 Bit Descriptions for DAC0DAT Bits Bit Name Description Reset...

Page 54: ...Description Reset Access 31 28 RESERVED Reserved Write 0 0x0 R 27 16 DAC3_DAT DAC3 data 0x0 RW 15 0 RESERVED Reserved Write 0 0x0 R DAC4 Data Register Address 0x40086414 Reset 0x00000000 Name DAC4DAT...

Page 55: ...0x0 R DAC6 Data Register Address 0x4008641C Reset 0x00000000 Name DAC6DAT Table 60 Bit Descriptions for DAC6DAT Bits Bit Name Description Reset Access 31 28 RESERVED Reserved Write 0 0x0 R 27 16 DAC6_...

Page 56: ...nterrupts are serviced 15 SYSTICK Programmable System tick timer The peripheral interrupts are controlled by the NVIC and are listed in Table 63 All interrupt sources can wake up the device from Mode...

Page 57: ...2 PWM PAIR1 Yes No 53 PWM PAIR2 Yes No 54 PWM PAIR3 Yes No Internally to the ARM Cortex M3 processor the highest user programmable priority 0 is treated as fourth priority after a reset an NMI and a h...

Page 58: ...Table 63 RW 0xE000E184 ICER1 Clear IRQ32 to IRQ54 by setting the appropriate bit Each bit corresponds to Interrupt 32 to Interrupt 54 in Table 63 RW 0xE000E200 ISPR0 Set IRQ0 to IRQ31 pending Each bi...

Page 59: ...the always on section and allows external interrupt to wake up the device when in hibernate mode Ensure that the associated GPxIE register bit is enabled for the required external interrupt input The...

Page 60: ...IRQ2MDE External Interrupt 2 mode registers 0x0 RW 000 rising edge 001 falling edge 010 rising or falling edge 011 high level 100 low level 101 falling edge same as 001 110 rising or falling edge same...

Page 61: ...terrupt 6 mode registers 0x0 RW 000 rising edge 001 falling edge 010 rising or falling edge 011 high level 100 low level 101 falling edge same as 001 110 rising or falling edge same as 010 111 high le...

Page 62: ...rrupt 8 Set to 1 to clear an internal interrupt flag Cleared automatically by hardware 0x0 RW 7 IRQ7 External Interrupt 7 Set to 1 to clear an internal interrupt flag Cleared automatically by hardware...

Page 63: ...n a value written to the low voltage die this interrupt is asserted Low Voltage Die Interrupt 1 is more flexible than Low Voltage Interrupt 0 The key differences are as follows Low Voltage Die Interru...

Page 64: ...ESERVED Reserved 0x0 RW 10 SEL_DCOMP_0 Write 1 to this bit to enable digital comparator interrupt for Interrupt Pin 0 0x0 RW 9 SEL_ADC_SEQ_0 Write 1 to this bit to enable ADC sequence conversion inter...

Page 65: ...ng to this register 0x2009 must be written to RSTKEY followed by 0x0426 After the two keys are written to RSTKEY RSTCFG must be immediately written The RSTSTA register stores the cause for the reset u...

Page 66: ...set Ensure that LVRST 0 1 1 high voltage die retain status after watchdog or software reset Ensure that LVRST 0 0 0 GPIO_PLA_RETAIN GPIO PLA retain their status after watchdog or software reset 0x0 RW...

Page 67: ...PI0 Tx 1 SPI0 Rx 2 SPI1 Tx 3 SPI1 Rx 4 UART Tx 5 UART Rx 6 I2 C0 slave Tx 7 I2 C0 slave Rx 8 I2 C0 master 9 I2 C1 slave Tx 10 I2 C1 slave Rx 11 I2 C1 master 12 ADC 13 Flash The channels are connected...

Page 68: ...ta structure is shown in Table 82 Table 81 Channel Control Data Structure Offset Name Description 0x00 SRC_END_PTR Source end pointer 0x04 DST_END_PTR Destination end pointer 0x08 CHNL_CFG Control dat...

Page 69: ...t the DST_END_PTR memory location contains Half Word 00 Reserved 01 Half word 10 Word 11 No increment Address remains set to the value that the DST_END_PTR memory location contains Word 00 Reserved 01...

Page 70: ...memory with the N_MINUS_1 field changed to reflect the number of transfers yet to be completed When the whole DMA cycle is complete the CYCLE_CTRL bits are made invalid to indicate the completion of...

Page 71: ...or alternate control data structure work exactly the same as a basic DMA transfer Memory Scatter Gather CHNL_CFG 2 0 100 or 101 In memory scatter gather mode the controller must be configured to use...

Page 72: ...r a basic cycle or the DMA reads an invalid data structure Table 85 lists the fields of the CHNL_CFG memory location for the primary data structure which must be programmed with constant values for th...

Page 73: ...W 0x4001004C DMAERRCLR DMA per channel bus error 0x00000000 RW 0x40010800 DMABSSET DMA channel bytes swap enable set 0x00000000 RW 0x40010804 DMABSCLR DMA channel bytes swap enable clear 0x00000000 W...

Page 74: ...01000C Reset 0x00000100 Name DMAADBPTR The DMAADBPTR read only register returns the base address of the alternate channel control data structure This register removes the necessity for application sof...

Page 75: ...ar REQ_MASK_SET bits in DMARMSKSET This register enables DMA requests from peripherals by clearing the mask set in the DMARMSKSET register Each bit of the register represents the corresponding channel...

Page 76: ...nsfers Table 96 Bit Descriptions for DMAALTSET Bits Bit Name Description Reset Access 31 14 RESERVED Reserved Undefined 0x0 R 13 0 CHPRIALTSET Control structure status select alternate structure Retur...

Page 77: ...fault priority level The DMAPRICLR write only register enables the user to configure a DMA channel to use the default priority level Each bit of the register represents the corresponding channel numbe...

Page 78: ...nabled When written Bit C 0 no effect Use the DMABSCLR register to disable byte swap on Channel C Bit C 1 enables byte swap on Channel C DMA Channel Bytes Swap Enable Clear Register Address 0x40010804...

Page 79: ...hole is open for access command fail and command complete status bits A cache is provided to speed up execution Commands The flash controller supports the following commands Write command 64 bits per...

Page 80: ...enabled The kernel code cannot be accessed by the user The user can read 16 bytes of Flash 0 information space at Address 0x407E8 to Address 0x407F7 These locations contain MANFID0 MANFID1 and the nex...

Page 81: ...rograms 64 bits of data To write to a flash location the following sequence is required 1 Write the address of the flash location to FEEFLADR 2 Write the 64 bits of data to FEEFLDATA0 and FEEFLDATA1 3...

Page 82: ...rc int iLen int aiData int i1 i2 iCrc iCrc 0xffffffff Seed value for i1 0 i1 iLen i1 Starting at lowest address for i2 31 i2 0 i2 MSB first iCrc 1 Left shift if aiData i1 1 i2 iCrc 0x00800063 Polynomi...

Page 83: ...es to these MMRs The user key is 0xF123F456 This key must be entered to run certain user commands write to certain locations in flash or to enable write access to FEECON1 Once entered the key remains...

Page 84: ...write is aborted via a system interrupt FEESTA 5 4 indicates an abort FEESTA 5 4 11 Depending on the state that a write cycle is in when the abort asserts the write cycle may or may not complete If t...

Page 85: ...ution The instruction cache is configured and set up by default If the user writes code to the flash the user must perform a chip reset to ensure that old cached data is cleared and that the new code...

Page 86: ...pADI_DMA DMAENSET 0x2000 pADI_FEE FEEFLADR uiAdr pADI_FEE FEEKEY 0xF123F456 pADI_FEE FEECON1 FEECON1_KHDMA_EN Enable Flash DMA mode void FLASHDMAWRITE unsigned char pucTX_DMA unsigned int iNumVals Dm...

Page 87: ...ster interrupt enable register 0x00000000 RW 0x40018008 FEECMD Command register 0x00000000 RW 0x4001800C FEEFLADR Flash address keyhole register 0x00000000 RW 0x40018010 FEEFLDATA0 Flash data register...

Page 88: ...detected for one flash location during read from Flash 1 The error is corrected 11 1 bit and 2 bit error detected ERR1BIT_2BIT During the read 1 bit error and 2 bit errors are detected in Flash 1 24...

Page 89: ...during the signature check 01 error detected ERRDETECTED 2 bit error detected in one or more flash locations during the signature command The errors are not corrected 10 error corrected ERRCORRECTED 1...

Page 90: ...ered via the command register 0x0 R Command Control Register Interrupt Enable Register Address 0x40018004 Reset 0x00000000 Name FEECON0 Table 106 Bit Descriptions for FEECON0 Bits Bit Name Description...

Page 91: ...he FEEKEY register 00100 WRITE Use this command to write to flash locations This command requires a user key for writing into write protection location and USERFAAKEY location No key is required for o...

Page 92: ...Name Description Reset Access 31 0 FLDATA1 FLDATA1 forms the upper 32 bit of the 64 bit data to be written to flash 0x0 RW Lower Page Address Register Address 0x40018018 Reset 0x00000000 Name FEEADR0...

Page 93: ...re Register Address 0x40018034 Reset 0x0000000X Name FEESIG Table 116 Bit Descriptions for FEESIG Bits Bit Name Description Reset Access 31 24 RESERVED Returns 0x0 if read 0x0 R 23 0 SIGN 24 bit signa...

Page 94: ...Each bit corresponds to one interrupt listed in the interrupt vector table 0x0 RW ECC Enable Disable Error Response Register Address 0x40018064 Reset 0x00000000 Name FEEECCCONFIG This register is key...

Page 95: ...me Description Reset Access 31 20 RESERVED Reserved 0x0 R 18 DLOCK This bit is set when the data cache is locked and cleared when the data cache is unlocked 0x0 R 17 DEN If this bit is set the data ca...

Page 96: ...he initialization starts 0x0 RW 15 5 RESERVED Reserved 0x0 RW 4 IRDBUF If this bit is set for every AHB access a hit from the read buffer is not checked 0x0 RW 3 IWRBUF If this bit is set for every AH...

Page 97: ...FICATION Table 127 Silicon ID Register Summary Address Name Description Reset Access 0x40002024 CHIPID Digital die ID 0x0563 R 0x40082C30 LVID Low voltage die ID 0x0074 R REGISTER DETAILS SILICON IDEN...

Page 98: ...ped into four ports Port 0 Port 1 and Port 2 contains eight GPIOs and Port 3 contains four GPIOs Each GPIO can be configured as input output or fully open circuit and has an internal pull up programma...

Page 99: ...as an output To disable the input and not drive the pin set the open drain and drive Logic 1 External interrupts are not available when open drain is enabled If a pin is configured as an open drain o...

Page 100: ...0x0 I2 C0 SDA GP0CON 11 10 0x1 PLAO 3 GP0CON 11 10 0x3 P0 6 GPIO GP0CON 13 12 0x0 I2 C1 SCL GP0CON 13 12 0x1 PLAO 4 GP0CON 13 12 0x3 P0 7 GPIO GP0CON 15 14 0x0 I2 C1 SDA GP0CON 15 14 0x1 PLAO 5 GP0CON...

Page 101: ...9 8 0x3 P2 5 GPIO IRQ6 GP2CON 11 10 0x0 PWM7 GP2CON 11 10 0x2 PLAO 19 GP2CON 11 10 0x3 P2 6 GPIO IRQ7 GP2CON 13 12 0x0 PLAO 20 GP2CON 13 12 0x3 P2 7 GPIO IRQ8 GP2CON 15 12 0x0 PLAO 21 GP2CON 15 14 0x...

Page 102: ...IO Port 1 data out clear 0x00 W 0x40020058 GP1SET GPIO Port 1 data out set 0x00 W 0x40020060 GP1TGL GPIO Port 1 pin toggle 0x00 W 0x40020064 GP1ODE GPIO Port 1 open drain enable 0x00 RW 0x40020080 GP2...

Page 103: ...put Enable Registers Address 0x40020004 Reset 0x00 Name GP0OEN Address 0x40020044 Reset 0x00 Name GP1OEN Address 0x40020084 Reset 0x00 Name GP2OEN Table 133 Bit Descriptions for GP0OEN GP1OEN and GP2O...

Page 104: ...o drive the corresponding GPIO low 1 set by user code to drive the corresponding GPIO high GPIO Port Data Out Set Register Address 0x40020018 Reset 0x00 Name GP0SET Address 0x40020058 Reset 0x00 Name...

Page 105: ...ot use the bit band alias addresses for this register 0x00 W 0 clearing this bit has not effect 1 set by user code to invert the corresponding GPIO pin GPIO Port Open Drain Enable Registers Address 0x...

Page 106: ...0 RW 0 disable the output on P3 4 1 enable the output on P3 4 3 RESERVED Reserved 0x0 R 2 OEN Pin output drive enable 0x0 RW 0 disable the output on P3 2 1 enable the output on P3 2 1 OEN Pin output d...

Page 107: ...ut Reflects the state of P3 4 0xX R 3 RESERVED Reserved 0xX R 2 IN Registered data input Reflects the state of P3 2 0xX R 1 IN Registered data input Reflects the state of P3 1 0xX R 0 IN Registered da...

Page 108: ...the output high Do not use the bit band alias addresses for this register 0x0 W 0 clearing this bit has no effect 1 set by user code to drive P3 0 high GPIO Port 3 Data Out Clear Register Address 0x4...

Page 109: ...ng this bit has no effect 1 set by user code to invert P3 1 0 TGL Toggle the output of the port pin Do not use the bit band alias addresses for this register 0x0 W 0 clearing this bit has no effect 1...

Page 110: ...a stop condition and the bus becomes idle Figure 20 shows a typical I2 C transfer A master device can be configured to generate the serial clock The user programs the frequency in the serial clock div...

Page 111: ...ansfer by changing the R W bit without having to give up control of the bus An example of a transfer sequence is shown in Figure 22 This is generally used where the first data sent to the device sets...

Page 112: ...during a write sequence Slave Transfer Initiation If the slave enable bit I2CxSCON 0 SLVEN is set a slave transfer sequence is monitored for the device address in Register I2CxID0 Register I2CxID1 Reg...

Page 113: ...CL for a R W bit the slave returns a no acknowledge after the timeout period If the first byte is transmitted correctly in a slave Tx sequence but the Tx FIFO is empty for any subsequent bytes in the...

Page 114: ...s off To fully power down the I2 C block disable the clock to the I2 C section of the chip by setting CLKCON5 4 3 0x3 DMA Requests Four DMA channels are required to service the I2 C master and slave D...

Page 115: ...equest interrupt enable 0x0 RW 0 disable transmit request interrupt 1 enable transmit request interrupt 4 IENMRX Receive request interrupt enable 0x0 RW 0 disable receive request interrupt 1 enable re...

Page 116: ...sserts if the master is enabled MASEN 1 Use this bit to determine when it is safe to disable the master It can also wait for another master transaction to complete on the I2 C bus when this master los...

Page 117: ...ive Data Count Register Address 0x40003010 Reset 0x0000 Name I2CMRXCNT Table 157 Bit Descriptions for I2CMRXCNT Bits Bit Name Description Reset Access 15 9 RESERVED Reserved 0x0 R 8 EXTEND Extended re...

Page 118: ...ts of the address 0x0 RW Serial Clock Period Divisor Register Address 0x40003024 Reset 0x1F1F Name I2CDIV Table 161 Bit Descriptions for I2CDIV Bits Bit Name Description Reset Access 15 8 HIGH Serial...

Page 119: ...at 0 when it next goes to 0 0x0 RW 5 EARLYTXR Early transmit request mode Setting this bit enables a transmit request just after the positive edge of the direction bit SCL clock pulse 0x0 RW 4 GCSBCLR...

Page 120: ...f any type To clear write 1 to the GCSBCLR in the slave control register If it was a general call reset all registers are at their default values If it was a hardware general call the Rx FIFO holds th...

Page 121: ...TX Slave transmit register 0x0 RW Hardware General Call ID Register Address 0x40003038 Reset 0x0000 Name I2CALT Table 166 Bit Descriptions for I2CALT Bits Bit Name Description Reset Access 15 8 RESERV...

Page 122: ...Table 171 Bit Descriptions for I2CFSTA Bits Bit Name Description Reset Access 15 10 RESERVED Reserved 0x0 RW 9 MFLUSH Flush the master transmit FIFO 0x0 W 0 clearing to 0 has no effect 1 set to 1 to f...

Page 123: ...the negative edge of SCL when the slave Rx FIFO is full before sending acknowledge no acknowledge Stretching stops when slave Rx FIFO is no longer in an overflow condition or if a timeout occurs 0x0...

Page 124: ...x40003424 I2C1DIV Serial clock period divisor register 0x1F1F RW 0x40003428 I2C1SCON Slave control register 0x0000 RW 0x4000342C I2C1SSTA Slave I2 C status error IRQ register 0x0001 R 0x40003430 I2C1S...

Page 125: ...it request interrupt enable 0x0 RW 0 disable transmit request interrupt 1 enable transmit request interrupt 4 IENMRX Receive request interrupt enable 0x0 RW 0 disable receive request interrupt 1 enabl...

Page 126: ...asserts This bit only asserts if the master is enabled MASEN 1 Use this bit to determine when it is safe to disable the master It can also wait for another master transaction to complete on the I2 C b...

Page 127: ...e Data Count Register Address 0x40003410 Reset 0x0000 Name I2C1MRXCNT Table 179 Bit Descriptions for I2C1MRXCNT Bits Bit Name Description Reset Access 15 9 RESERVED Reserved 0x0 R 8 EXTEND Extended re...

Page 128: ...wer 8 bits of the address 0x0 RW Serial Clock Period Divisor Register Address 0x40003424 Reset 0x1F1F Name I2C1DIV Table 183 Bit Descriptions for I2C1DIV Bits Bit Name Description Reset Access 15 8 HI...

Page 129: ...r if SCL is 1 when it next goes to 0 hold it at 0 0x0 RW 5 EARLYTXR Early transmit request mode Setting this bit enables a transmit request just after the positive edge of the direction bit SCL clock...

Page 130: ...ear write 1 to the GCSBCLR in the slave control register If it was a general call reset all registers are at their default values If it was a hardware general call the Rx FIFO holds the second byte of...

Page 131: ...ransmit register 0x0 RW Hardware General Call ID Register Address 0x40003438 Reset 0x0000 Name I2C1ALT Table 188 Bit Descriptions for I2C1ALT Bits Bit Name Description Reset Access 15 8 RESERVED Reser...

Page 132: ...FSTA Table 193 Bit Descriptions for I2C1FSTA Bits Bit Name Description Reset Access 15 10 RESERVED Reserved 0x0 RW 9 MFLUSH Flush the master transmit FIFO 0x0 W 0 clearing to 0 has no effect 1 set to...

Page 133: ...tched from the negative edge of SCL when the slave Rx FIFO is full before sending acknowledge no acknowledge Stretching stops when the slave Rx FIFO is no longer in an overflow condition or if a timeo...

Page 134: ...before enabling the SPI peripheral and that the internal pull up resistors on the SPI pins must be disabled via the GPxPUL registers when using the SPI MISO Master In Slave Out Pin The MISO pin is con...

Page 135: ...ve overflow interrupts SPIxCON 12 can be set and the receive data is not saved to the Rx FIFO Similarly when the user wants to only receive data and does not want to write data to the Tx FIFO SPIxCON...

Page 136: ...discarded if there is no space left in the FIFO When the RXOF is set the contents of the SPI Rx FIFO are undefined and its contents must be discarded by user code Full Duplex Operation Simultaneous r...

Page 137: ...SPIxCON 6 is cleared the Rx FIFO status causes the interrupt SPIxCON 15 14 control when the interrupt occurs The interrupt is cleared by a read of SPIxSTA The status of this interrupt can be read by...

Page 138: ...by user code and an overflow interrupt is generated To avoid generating overflow interrupts set the Rx FIFO flush bit or disable the SPI interrupt in the NVIC If only the DMA receive request SPIxDMA...

Page 139: ...buffer must be of the same size as SPI1CNT to generate a DMA interrupt when the transfer is complete SPI AND POWER DOWN MODES In master mode before entering power down mode it is recommended to disabl...

Page 140: ...ame 0x0 RC 0 cleared to 0 when the status register is read 1 set to 1 when there was a falling edge in the CS line when the device was in master mode continuous transfer high frequency mode and CSIRQ_...

Page 141: ...sabled 0x0 R 7 0 DATA_BYTE_1 8 bit receive buffer 0x0 R Transmit Register Address 0x4002C008 Reset 0x0000 Name SPI0TX Table 200 Bit Descriptions for SPI0TX Bits Bit Name Description Reset Access 15 8...

Page 142: ...high either the last transmitted value or 0x00 is transmitted depending on the ZEN bit Any writes to the Tx FIFO are ignored while this bit is set 12 RFLUSH SPI Rx FIFO flush enable 0x0 RW 0 clear th...

Page 143: ...enable the SPI SPI DMA Enable Register Address 0x4002C014 Reset 0x0000 Name SPI0DMA Table 203 Bit Descriptions for SPI0DMA Bits Bit Name Description Reset Access 15 3 RESERVED Reserved 0x0 R 2 IENRXDM...

Page 144: ...RC 0 cleared to 0 when the status register is read 1 set to 1 when there was a falling edge in CS line when the device was in master mode continuous transfer high frequency mode and CSIRQ_EN was asse...

Page 145: ...bled 0x0 R 7 0 DATA_BYTE_1 8 bit receive buffer 0x0 R Transmit Register Address 0x40030008 Reset 0x0000 Name SPI1TX Table 208 Bit Descriptions for SPI1TX Bits Bit Name Description Reset Access 15 8 DM...

Page 146: ...igh either the last transmitted value or 0x00 is transmitted depending on the ZEN bit Any writes to the Tx FIFO are ignored while this bit is set 12 RFLUSH SPI Rx FIFO flush enable 0x0 RW 0 clear this...

Page 147: ...nable the SPI SPI DMA Enable Register Address 0x40030014 Reset 0x0000 Name SPI1DMA Table 211 Bit Descriptions for SPI1DMA Bits Bit Name Description Reset Access 15 3 RESERVED Reserved 0x0 R 2 IENRXDMA...

Page 148: ...riting to the transmit holding register COMTX After a synchronization delay the data is moved to the internal transmit shift register TSR where it is shifted out at a baud bit rate equal to UCLK CDPCL...

Page 149: ...g These errors are not detected in the hardware Enable Disable Bit Before the ADuCM310 enters power down mode it is recommended to disable the serial interfaces A bit is provided in the UART control r...

Page 150: ...A Rx transfers void UARTDMAREAD unsigned char pucRX_DMA unsigned int iNumVals DmaDesc Desc Common configuration of all the descriptors used here Desc ctrlCfg bits cycle_ctrl DMA_BASIC desc ctrlcfg bit...

Page 151: ...A Tx transfers void UARTDMAWRITE unsigned char pucTX_DMA unsigned int iNumVals DmaDesc Desc Common configuration of all the descriptors used here Desc ctrlCfg Bits cycle_ctrl DMA_BASIC Desc ctrlCfg Bi...

Page 152: ...ters If these registers are written to the user accesses the transmit holding register COMTX If these registers are read from the user accesses the receive buffer register COMRX Table 214 Bit Descript...

Page 153: ...nterrupt enabled 1 ETBEI Transmit buffer empty interrupt 0x0 RW 0 interrupt disabled 1 interrupt enabled 0 ERBFI Receive buffer full interrupt 0x0 RW 0 interrupt disabled 1 interrupt enabled Interrupt...

Page 154: ...evaluated on data received 0x0 RW 0 send 1 stop bit regardless of the word length WLS 1 send a number of stop bits based on the word length Transmit 1 5 stop bits if the word length is 5 bits WLS 00 o...

Page 155: ...eceived word 2 PE Parity error If set this bit self clears after COMLSR is read 0x0 RC 0 no parity error is detected 1 a parity error has occurred on a received word 1 OE Overrun error If set this bit...

Page 156: ...the scratch register does not affect UART functionality or performance Only 8 bits of this register are implemented Bits 15 8 are read only and always return 0x00 when read SCR is writable with any v...

Page 157: ...FXTAL OR INTERNAL 16MHz OSCILLATOR HFOSC DEPENDS ON THE VALUE IN CLKCON0 11 CLOCK SOURCES 11461 025 Figure 27 General Purpose Timers Block Diagram GENERAL PURPOSE TIMERS OVERVIEW Timer 0 Timer 1 and T...

Page 158: ...s reloaded automatically when generating the interrupt signal If TxCON 7 is set to 1 the counter is also reloaded when user code writes TxCLRI This allows user changes to the TxLD to take effect immed...

Page 159: ...unction Event Select Bits EVENT Bits in TxCON Register TxCON 11 8 Timer 0 Capture Source Timer 1 Capture Source Timer 2 Capture Source 0000 Wake Up Timer External Interrupt 4 External Interrupt 7 0001...

Page 160: ...ions for T0VAL Bits Bit Name Description Reset Access 15 0 VAL Current count Reflects the current up down counter value Value delayed two PCLK cycles due to clock synchronizers 0x0 R Control Register...

Page 161: ...up 1 0 PRE Prescaler These bits control the prescaler division factor applied to the selected clock of the timer If CLK Source 0 or CLK Source 1 are selected a prescaler value of 0 means divide by 4...

Page 162: ...timer clock domain 6 BUSY Timer busy This bit informs the user that a write to T0CON is still crossing into the timer clock domain Check this bit after writingT0CON and suppress further writes until...

Page 163: ...or T1VAL Bits Bit Name Description Reset Access 15 0 VAL Current count Reflects the current up down counter value Value delayed two PCLK cycles due to clock synchronizers 0x0 R Control Register Addres...

Page 164: ...1 0 PRE Prescaler These bits control the prescaler division factor applied to the selected clock of the timer If CLK Source 0 or CLK Source 1 are selected the prescaler value of 0 means divide by 4 o...

Page 165: ...timer clock domain 6 BUSY Timer busy This bit informs the user that a write to T1CON is still crossing into the timer clock domain Check this bit after writingT1CON and suppress further writes until...

Page 166: ...or T2VAL Bits Bit Name Description Reset Access 15 0 VAL Current count Reflects the current up down counter value Value delayed two PCLK cycles due to clock synchronizers 0x0 R Control Register Addres...

Page 167: ...p 1 0 PRE Prescaler These bits control the prescaler division factor applied to the selected clock of the timer If CLK Source 0 or CLK Source 1 are selected the prescaler value of 0 means divide by 4...

Page 168: ...e timer clock domain 6 BUSY Timer busy This bit informs the user that a write to T2CON is still crossing into the timer clock domain Check this bit after writing T2CON and suppress further writes unti...

Page 169: ...ERATION The watchdog timer is enabled by default after a reset User code must disable the watchdog timer at the start of user code when debugging or if the watchdog timer is not required T3CON 0x00 Di...

Page 170: ...lt 4 RESERVED Reserved 0x0 R 3 2 PRE Prescaler 0x2 RW 00 DIV1 Source Clock 1 01 DIV16 Source Clock 16 10 DIV256 Source Clock 256 default 11 DIV4096 Source Clock 4096 1 IRQ Timer interrupt 0x0 RW 0 DIS...

Page 171: ...utomatically in hardware if T3CON 5 has been set by user code Cleared by default and until user code sets T3CON 5 0x0 R 3 CON T3CON write synchronization in progress 0x0 R 0 internal bus andTimer 3 cl...

Page 172: ...and then restarts at 0x00000000 In periodic mode the timer counts from 0x00000000 to T4WUFD T4WUFD0 and T4WUFD1 In addition the wake up timer has four specific time fields to compare with the wake up...

Page 173: ...et STOPINC T4CON 11 1 while the timer is running The new T4INC value takes effect after the next Wake Up Field A interrupt If the user is writing to this register while the timer is enabled set the ST...

Page 174: ...ast significant 16 bits 0x0000 R 0x40002504 T4VAL1 Current count value most significant 16 bits 0x0000 R 0x40002508 T4CON Control register 0x0040 RW 0x4000250C T4INC 12 bit interval for Wake Up Field...

Page 175: ...s mode the timer counts up to T4WUFD 1 FREERUN Set by user to operate in free running mode default 5 4 RESERVED Reserved Write these bits 0 0x0 RW 3 FREEZE Freeze enable 0x0 RW 0 DIS Cleared by user t...

Page 176: ...eld C 0x3FFF RW Wake Up Field D Most Significant 16 Bits Register Address 0x40002524 Reset 0x0000 Name T4WUFD1 Table 263 Bit Descriptions for T4WUFD1 Bits Bit Name Description Reset Access 15 0 T4WUFD...

Page 177: ...e to the corresponding bit in T4CLRI 0x0 R 1 WUFB T4WUFB interrupt flag Set automatically to indicate a comparator interrupt has occurred Cleared automatically after a write to the corresponding bit i...

Page 178: ...2 Standard PWM5 Low side PWM output for Pair 2 Standard PWM6 High side PWM output for Pair 3 Standard PWM7 Low side PWM output for Pair 3 Standard PWM OPERATION In all modes the PWMxCOMx MMRs control...

Page 179: ...WM timer reaches the count value stored in this register PWM1COM0 0x020 PWM2 output goes high when the PWM timer reaches the count value stored in this register PWM1COM1 0x024 PWM2 output goes low whe...

Page 180: ...programmed in the PWM0 registers PWM INTERRUPT GENERATION PWM Trip Function Interrupt When the PWM trip function is enabled TRIPEN PWMCON1 6 and the PWM trip input signal goes low falling edge the PWM...

Page 181: ...x40024040 PWM3COM0 Compare Register 0 for PWM6 and PWM7 0x0000 RW 0x40024044 PWM3COM1 Compare Register 1 for PWM6 and PWM7 0x0000 RW 0x40024048 PWM3COM2 Compare Register 2 for PWM6 and PWM7 0x0000 RW...

Page 182: ...riptions for PWMCON1 Bits Bit Name Description Reset Access 15 7 RESERVED Reserved Return 0 on reads 0x00 Reserved 6 TRIP_EN Set to enable PWM trip functionality 0x0 RW 5 0 RESERVED Reserved 0x0 Reser...

Page 183: ...eset 0x0000 Name PWM1LEN Table 282 Bit Descriptions for PWM1LEN Bits Bit Name Description Reset Access 15 0 LEN Period value 0x0 RW Compare Register 0 for PWM4 and PWM5 Address 0x40024030 Reset 0x0000...

Page 184: ...000 Name PWM3COM1 Table 288 Bit Descriptions for PWM3COM1 Bits Bit Name Description Reset Access 15 0 COM1 Compare Register 1 data 0x0 RW Compare Register 2 for PWM6 and PWM7 Address 0x40024048 Reset...

Page 185: ...K x ELEMENT 3 BLOCK x ELEMENT 5 BLOCK x ELEMENT 7 OUTPUT ELEMENT n WHERE BLOCK x IS BLOCK 0 OR BLOCK 1 PLA_ELEMn IS THE MMR CONTROLLING ELEMENT n n 0 TO 15 NC NO CONNECTION BLOCK x ELEMENT 0 BLOCK x E...

Page 186: ...configuration of these two multiplexers can be found in the PLA_ELEMn configuration register A complete list of the possible connections are available in Table 292 and Table 293 The four blocks can b...

Page 187: ...NT n 16 BLOCK 1 ELEMENT 7 ELEMENT 15 BLOCK 3 ELEMENT 7 ELEMENT 31 2 4 BLOCK 0 ELEMENT 0 ELEMENT 0 0 4 BLOCK 0 ELEMENT 7 ELEMENT 7 4 BLOCK 1 ELEMENT 0 ELEMENT 8 4 BLOCK 2 ELEMENT 7 ELEMENT 23 2 4 0 BLO...

Page 188: ...nt 18 Element 26 Element 26 10 Element 4 Element 4 Element 12 Element 12 Element 20 Element 20 Element 28 Element 28 11 Element 6 Element 6 Element 14 Element 14 Element 22 Element 22 Element 30 Eleme...

Page 189: ...it Descriptions for PLA_ELEMn Bits Bit Name Description Reset Access 15 11 RESERVED Not used 0x00 Reserved 10 9 MUX0 Even element feedback selection in respective block 0x0 RW 00 feedback from Element...

Page 190: ...0 GPIO clock on P2 0 011 HCLK 100 MOSC 101 Timer 0 110 Timer 2 111 KOSC 11 RESERVED Not used 0x0 Reserved 10 8 BLOCK2 Clock select for Block 2 0x0 RW 000 GPIO clock on P0 3 001 GPIO clock on P1 1 010...

Page 191: ...me PLA_IRQ1 Table 299 Bit Descriptions for PLA_IRQ1 Bits Bit Name Description Reset Access 15 13 RESERVED Not used 0x0 Reserved 12 IRQ3_EN IRQ3 enable 0x0 RW 0 disable IRQ3 interrupt 1 enable IRQ3 int...

Page 192: ...ps Semiconductors now NXP semiconductors ESD Caution ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features pate...

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