ADuCM310 Hardware Reference Manual
UG-549
Rev. C | Page 113 of 192
In the slave, if there is no valid data to transmit when the Tx shifter is loaded, the transmit underflow status bit asserts (I2CxMSTA[12],
ISCxSSTA[1]). In slave mode, the Tx FIFO must be loaded with a byte before the falling edge of SCL before the acknowledge/no acknowledge
is asserted.
If the Tx FIFO is empty on the falling edge of SCL for a R/W bit, the slave returns a no acknowledge because the slave in this case controls
the acknowledge/no acknowledge.
If the first byte is transmitted correctly in a slave Tx sequence but the Tx FIFO is empty for any subsequent bytes in the same transfer, the
slave returns the previous transmitted byte. This operation is due to the master having control of the acknowledge/no acknowledge during
a slave transfer sequence.
The master generates a stop condition if there is no data in the transmit FIFO and the master is writing data.
The receive data path consists of a master and slave Rx FIFO (I2CxMRX and I2CxSRX), each two bytes deep. The receive request interrupt bit
(I2CxMSTA[3] or I2CxSSTA[3]) indicates whether there is valid data in the Rx FIFO. Data is loaded into the Rx FIFO after each byte is received.
If valid data in the Rx FIFO is overwritten by the Rx shifter, the receive overflow status bit is asserted (I2CxMSTA[9] or I2CxSSTA[4]).
Automatic Clock Stretching
The
supports automatic clock stretching in both master and slave modes.
It is recommended that automatic clock stretching be enabled, especially in slave mode.
A timeout feature is added to ensure that the I
2
C block never erroneously holds the SCL pin low indefinitely. A separate status pin for
master and slave mode indicates if stretch timeout occurred.
The I2CxASSCL register controls automatic clock stretching. If automatic clock stretching is enabled, the I
2
C hardware holds the SCL pin
low after the falling edge of SCL before an acknowledge/no acknowledge during the following conditions:
•
Tx FIFO is empty when a valid read request is active for the master or slave.
•
If at the end of the timeout period, the Tx FIFO is still empty, the following occurs:
•
If the Tx FIFO is empty on the falling edge of SCL for a R/W bit, the slave returns a no acknowledge after the timeout
period.
•
If the first byte is transmitted correctly in a slave Tx sequence but the Tx FIFO is empty for any subsequent bytes in the
same transfer with clock stretch enabled, the slave returns the previous transmitted byte at the end of the timeout period.
•
Rx FIFO is full when another byte is about to be received. If the Rx FIFO has still not been read at the end of the timeout period, a
no acknowledge is returned and the master ends the sequence with a stop condition.
It is not recommended to use the I2CxSCON[6] clock stretching method when using automatic clock stretching.
Master No Acknowledge
When receiving data, the master responds with a no acknowledge if its FIFO is full and an attempt is made to write another byte to the
FIFO. This last byte received is not written to the FIFO and is lost.
No Acknowledge from the Slave
If the slave does not want to acknowledge a read access, then simply not writing data into the slave transmit FIFO results in a
no acknowledge.
If the slave does not want to acknowledge a master write, assert the no acknowledge bit (NACK) in the slave control register, I2CxSCON[7].
Normally, the slave acknowledges all bytes that are written into the receive FIFO. If the receive FIFO fills up, the slave cannot write further
bytes to it, and it does not acknowledge the byte that was not written to the FIFO. The master must then stop the transaction.
The slave does not acknowledge a matching device address if the read/write bit is set and the transmit FIFO is empty. Therefore, there is
very little time for the microcontroller to respond to a slave transmit request and the assertion of the acknowledge. It is recommended that
EARLYTXR, I2CxSCON[5], be asserted for this reason.
General Call
An I
2
C general call is for addressing every device on the I
2
C bus. A general call address is 0x00 or 0x01. The first byte, the address byte, is
followed by a command byte.
If the address byte is 0x00, Byte 2 (the command byte) can be one of the following:
•
0x6: the I
2
C interface (master and slave) is reset. The general call interrupt status asserts, and the general call ID bits, GCID
(I2CxSSTA[9:8]), are 0x1. User code must take corrective action to reset the entire system or simply to reenable the I
2
C interface.
•
0x4: the general call interrupt status bit is asserted, and the general call ID bits (GCID) are 0x2.
