Analog Devices ADuCM310, Hardware Reference Manual

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ADuCM310 Hardware Reference Manual UG-549
Rev. C | Page 131 of 192
Bits Bit Name Description Reset Access
1 STXUR Slave transmit FIFO underflow. This bit is set if a master requests data from
the device, and the Tx FIFO is empty for the rising edge of SCL. 0x0 RC
0 STXFSEREQ Slave Tx FIFO status or early request. If EARLYTXR = 0, this bit is asserted
whenever the slave Tx FIFO is empty. If EARLYTXR = 1, TXFSEREQ is set when
the direction bit for a transfer is received high. It asserts on the positive edge
of the SCL clock pulse that clocks in the direction bit (if the device address
also matches). It only asserts once for a transfer. It is cleared when read if
EARLYTXR is asserted.
0x1 RW
Slave Receive Register
Address: 0x40003430, Reset: 0x0000, Name: I2C1SRX
Table 186. Bit Descriptions for I2C1SRX
Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved 0x0 R
[7:0] I2CSRX Slave receive register 0x0 R
Slave Transmit Register
Address: 0x40003434, Reset: 0x0000, Name: I2C1STX
Table 187. Bit Descriptions for I2C1STX
Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved 0x0 R
[7:0] I2CSTX Slave transmit register 0x0 RW
Hardware General Call ID Register
Address: 0x40003438, Reset: 0x0000, Name: I2C1ALT
Table 188. Bit Descriptions for I2C1ALT
Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved. 0x0 R
[7:0] ALT Slave alt. This register is used in conjunction with I2CSCON[3] to match a
master generating a hardware general call. It is used in the case where a
master device cannot be programmed with a slave address and instead the
slave must recognize the master address.
0x0 RW
First Slave Address Device ID Register
Address: 0x4000343C, Reset: 0x0000, Name: I2C1ID0
Table 189. Bit Descriptions for I2C1ID0
Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved. 0x0 R
[7:0] ID0 Slave device ID 0. I2CID0[7:1] is programmed with the device ID. I2CID0[0] is
don't care. See the ADR10EN bit in the slave control register to see how this
register is programmed with a 10-bit address.
0x0 RW
Second Slave Address Device ID Register
Address: 0x40003440, Reset: 0x0000, Name: I2C1ID1
Table 190. Bit Descriptions for I2C1ID1
Bits Bit Name Description Reset Access
[15:8] RESERVED Reserved. 0x0 R
[7:0] ID1 Slave device ID 1. I2CID1[7:1] is programmed with the device ID. I2CID1[0] is
don't care. See the ADR10EN bit in the slave control register to see how this
register is programmed with a 10-bit address.
0x0 RW