UG-549
ADuCM310 Hardware Reference Manual
Rev. C | Page 30 of 192
ADC Sequencer Control Register
Address: 0x40086088, Reset: 0x00000000, Name: ADCSEQ
Table 16. Bit Descriptions for ADCSEQ
Bits
Bit Name
Description
Reset
Access
31
ST
Sequence restart. Forces sequence to start at first channel when sequence
is working.
0x0
W
1: set to 1 to restart the sequencer. Cleared after writing 1.
30
EN
Sequence enable.
0x0
W
1: set to 1 to enable the sequencer.
29
STALL_SEQ
Status bit for ADC sequencer.
0x0
RW
0: ADC sequencer is running normally or not enabled.
1: ADC is being stalled. Set as part of the sequencer stall procedure.
[28:0]
CH
Select channels included in sequence operation. For each channel:
0x0
RW
0: channel is skipped.
1: channel is included in the sequence.
Each bit corresponds to an ADC channel as defined by ADCCHA[4:0]. For
example, a value of 0x33 (00110011) includes AIN0, AIN1, AIN4, and AIN5 in the
sequence and excludes all other channels. When using the sequencer with the
input buffer enabled and with chop mode enabled, ensure an odd number of
channels are enabled in the sequence (for example, 5, 7, or 9). Two consecutive
sequences are required with the input buffer enabled with chopping. Average
the two results for each enabled channel after the second sequence for the
final result.
ADC Sequencer Stall Status Register
Address: 0x40086084, Reset: 0x00000001, Name: ADCSEQS
Table 17. Bit Descriptions for ADCSEQS
Bits
Bit Name
Description
Reset
Access
[31:3]
RESERVED
Reserved.
0x0000000
R
2
SEQSTA
Sequence status.
0x0
R
1: busy. For a single sequence, the sequencer is converting input channels.
For repeated sequences, the sequencer is converting channels or is in the
delay period waiting to start another sequence.
0: idle. Sequences have completed.
1
STALLSEQ
Stall sequencer status bit.
0x0
R
0: sequencer is running.
1: sequencer is in the stalling phase.
0
STALLCNV
Stall ADC conversion status bit.
0x1
R
0: ADC single or repeated conversions running.
1: ADC conversions are stalling.
ADC Sequencer Configuration Register
Address: 0x4008608C, Reset: 0x00011111111, Name: ADCSEQC
Table 18. Bit Descriptions for ADCSEQC
Bits
Bit Name
Description
Reset
Access
[31:28]
RESERVED
Reserved.
0x00
R
[27:20]
T
Define programmable delay of 0 to 254 between sequences. A delay of 255
causes a halt after one sequence. Set ADCSEQ[30] if another sequence is
required. If the ADC input buffer is used in chop mode, ensure to use a
value of <255.
0xFF
RW
[19:15]
DIF6
Selects differential mode negative input for AIN6 in the sequence.
0x11
RW
0x11: Channel 6 is single-ended.
[14:10]
DIF4
Selects differential mode negative input for AIN4 in the sequence.
0x11
RW
0x11: Channel 4 is single-ended.
