UG-549
ADuCM310 Hardware Reference Manual
Rev. C | Page 110 of 192
I
2
C SERIAL INTERFACE
I
2
C FEATURES
The I
2
C interface has the following features:
•
Master or slave mode with 2-byte transmit and receive FIFOs
•
Supports
•
7-bit and 10-bit addressing modes
•
Four 7-bit device addresses or one 10-bit address and two 7-bit addresses in the slave
•
Repeated starts in master and slave modes
•
Clock stretching supported for the slave and master
•
Master arbitration
•
Continuous read mode for the master or up to 512 bytes fixed read
•
Internal and external loopback
•
Support for DMA in master and slave modes
•
Software control on the slave of no acknowledge (NACK) signal
I
2
C OVERVIEW
The I
2
C data transfer uses a serial clock pin (SCL) and a serial data pin (SDA). The pins are configured in a wired-AND’ed format that
allows arbitration in a multiple master system.
The transfer sequence of an I
2
C system consists of a master device initiating a transfer by generating a start condition while the bus is idle.
The master transmits the slave device address and the direction of the data transfer during the initial address transfer. If the master does
not lose arbitration and the slave acknowledges the initial address transfer, the data transfer is initiated. This continues until the master
issues a stop condition and the bus becomes idle. Figure 20 shows a typical I
2
C transfer.
A master device can be configured to generate the serial clock. The user programs the frequency in the serial clock divisor register, I2CxDIV
(where x is 0 for I
2
C0 and 1 for I
2
C1). The master channel can be set to operate in fast mode (400 kHz) or in standard mode (100 kHz).
MSB
START
BIT
SCL
ACK
BIT
ACK
BIT
STOP
BIT
SLAVE ADDRESS
SDA
MSB
LSB
LSB
DATA
1
1
7
8
8
9
9
2
3 TO 6
2 TO 7
R/W
1
1461-
018
Figure 20. Typical I
2
C Transfer Sequence
The user programs the I
2
C bus peripheral address in the I
2
C bus system. This ID can be modified any time a transfer is not in progress.
The user can set up to four slave addresses that are recognized by the peripheral. The peripheral is implemented with a 2-byte FIFO for
each transmit and receive shift register. The IRQ and status bits in the control registers are available to signal to the processor core when
the FIFOs must be serviced.
I
2
C OPERATION
I
2
C Startup
The following steps are required to set the I
2
C peripheral running:
1.
Configure I
2
C clock in CLKCON1[10:8], CLKCON5[4] for I
2
C1, and CLKCON5[3] for I
2
C0.
2.
Configure digital pins for I
2
C operation via the GP0CON register (P0.4/P0.5, P0.6/P0.7).
3.
Configure I
2
C registers as required for slave or master operation.
4.
Enable the I
2
C slave or master interrupt source as required.
Note that the user must disable the internal pull-up resistors on the I
2
C pins via the GP0PUL register when using I
2
C.
