5-2
BRC-300/300P
BRU-300/300P
5-1-3. CC-91 Board
The CC-91 board comprises the following:
.
LVDS receiver (IC008)
.
Memory controller (IC007), FIFO memory (IC001 to
IC004)
.
Digital encoder (IC026)
for outputting an analog composite video signal and
analog S video signal (Y/C)
.
Synchronization circuit
.
VISCA interface (IC606, IC608)
Video Signal Processing
The LVDS receiver converts the LVDS signal sent from
the IF-944 board to 8-bit Y signal, 8-bit CbCr video data,
sync pulses (HD/VD/FLD), and 27 MHz clock, and then
sends them to the memory controller.
The memory controller has functions to the following
functions.
(1) Multiplex the input 13.5 MHz rate Y data and CbCr
data at 27 MHz rate.
(2) Write video data in the FIFO memory ICs in synchro-
nization with the 27 MHz clock from the LVDS
receiver.
(3) Read video data from the FIFO memory ICs in
synchronization with the 27 MHz read-clock divided
from the 54 MHz clock.
(4) Demultiplex the multiplexed video data into the
original 13.5 MHz rate Y and CbCr video data.
(5) Mix the character.
Each FIFO memory IC retains video data of one field. For
example, when video data is written in the order of FIFO 1
→
2
→
3
→
4
→
1 ... , the video data can be read in the
order of FIFO 3
→
4
→
1
→
2
→
3 ... . Though the BRC-
300/300P camera block has not an external sync function,
an external synchronization is given to the system by
providing a buffering function using FIFO memory ICs.
Further, the FIFO memory has a function to reverse video
data when writing, which enables the E. FLIP function.
E. FLIP function: A function to flip camera image vertically
The digital encoder encodes the 13.5 MHz rate Y and
CbCr video data from the memory controller to NTSC or
PAL composite signal, Y signal and C signal, using the 27
MHz clock and H SYNC/V SYNC signals. The encoder
then converts the encoded signals to an analog composite
signal and analog S video signals (Y/C).
Characters generated in the SY-314 board for menu
display are superimposed with video data in the digital
encoder.
Synchronization and Clock
The operation of the synchronization circuit during
operation of BRC-300/300P only differs from that with a
combination with BRBK-303 and BRU-300/300P.
.
During operation of BRC-300/300P only
A circuit centering the signal generator locking driver
IC014 becomes effective in this state. IC009 detects
whether the EXT SYNC signal has been input or not,
and IC014 recognizes external synchronization or
internal synchronization.
When the EXT SYNC signal has not been input (internal
synchronization), the INT VCO CONT signal sent from
the microcomputer on the SY-314 board via the D/A
converter IC025 controls the 54 MHz VCO.
When the EXT SYNC signal has been input (external
synchronization), IC014 phase-compares the H REF
signal sent from the memory controller with the EXT
SYNC signal to control the 54 MHz VCO. The crystal
oscillator X003 (or X002 in PAL system) generates
clock for the signal generator locking driver (BRC-300:
14.31818 M Hz, BRC-300P: 14.1875 MHz).
.
During operation with a combination with
BRBK-303 and BRU-300/300P
The following two types of 27 MHz clock are phase-
compared by IC019 to control the 54 MHz VCO.
- 27 MHz clock that is generated by the 54 MHz VCO
- 27 MHz clock that is divided in BRBK-303 from the
54 MHz clock sent from BRU-300/300P through the
optical fiver cable
VISCA Communication Interface
IC606 and IC608 are data transceivers using the VISCA
protocol. IC606 is used for the RS-232C interface, and
IC608 for the RS-422 interface. The microcomputer on the
SY-314 board controls data communication according to
baud rate 9600 bps or 38400 bps.
