97BPLC concepts
4.1 Execution of the user program
S7-1200 Programmable controller
System Manual, 11/2011, A5E02486680-05
79
Table 4- 6
System memory
7
6
5
4
3
2
1
0
Reserved
Value 0
Always off
Value 0
Always on
Value 1
Diagnostic status
indicator
1: Change
0: No change
First scan indicator
1: First scan after
startup
0: Not first scan
Clock memory configures a byte that cycles the individual bits on and off at fixed intervals.
Each clock bit generates a square wave pulse on the corresponding M memory bit. These
bits can be used as control bits, especially when combined with edge instructions, to trigger
actions in the user code on a cyclic basis.
Table 4- 7
Clock memory
Bit number
7
6
5
4
3
2
1
0
Tag name
Period (s)
2.0
1.6
1.0
0.8
0.5
0.4
0.2
0.1
Frequency (Hz)
0.5
0.625
1
1.25
2
2.5
5
10
Because clock memory runs asynchronously to the CPU cycle, the status of the clock memory can change several times
during a long cycle.
