97BPLC concepts
4.2 Data storage, memory areas, I/O and addressing
S7-1200 Programmable controller
System Manual, 11/2011, A5E02486680-05
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I_:P accesses are also restricted to the size of inputs supported by a single CPU, SB, or SM,
rounded up to the nearest byte. For example, if the inputs of a 2 DI / 2 DQ SB are configured
to start at I4.0, then the input points can be accessed as I4.0:P and I4.1:P or as IB4:P.
Accesses to I4.2:P through I4.7:P are not rejected, but make no sense since these points are
not used. Accesses to IW4:P and ID4:P are prohibited since they exceed the byte offset
associated with the SB.
Accesses using I_:P do not affect the corresponding value stored in the input process image.
Table 4- 10 Absolute addressing for I memory (immediate)
Bit
I[byte address].[bit address]:P
I0.1:P
Byte, Word, or Double word
I[size][starting byte address]:P
IB4:P, IW5:P, or ID12:P
Q (process image output): The CPU copies the values stored in the output process image to
the physical output points. You can access the output process image in bits, bytes, words, or
double words. Both read and write access is permitted for process image outputs.
Table 4- 11 Absolute addressing for Q memory
Bit
Q[byte address].[bit address]
Q1.1
Byte, Word, or Double word
Q[size][starting byte address]
QB5, QW10, QD40
By appending a ":P" to the address, you can immediately write to the physical digital and
analog outputs of the CPU, SB or SM. The difference between an access using Q_:P instead
of Q is that the data goes directly to the points being accessed in addition to the output
process image (writes to both places). This Q_:P access is sometimes referred to as an
"immediate write" access because the data is sent immediately to the target point; the target
point does not have to wait for the next update from the output process image.
Because the physical output points directly control field devices that are connected to these
points, reading from these points is prohibited. That is, Q_:P accesses are write-only, as
opposed to Q accesses which can be read or write.
Q_:P accesses are also restricted to the size of outputs supported by a single CPU, SB, or
SM, rounded up to the nearest byte. For example, if the outputs of a 2 DI / 2 DQ SB are
configured to start at Q4.0, then the output points can be accessed as Q4.0:P and Q4.1:P or
as QB4:P. Accesses to Q4.2:P through Q4.7:P are not rejected, but make no sense since
these points are not used. Accesses to QW4:P and QD4:P are prohibited since they exceed
the byte offset associated with the SB.
Accesses using Q_:P affect both the physical output as well as the corresponding value
stored in the output process image.
Table 4- 12 Absolute addressing for Q memory (immediate)
Bit
Q[byte address].[bit address]:P
Q1.1:P
Byte, Word, or Double word
Q[size][starting byte address]:P
QB5:P, QW10:P or QD40:P
M (bit memory area): Use the bit memory area (M memory) for both control relays and data
to store the intermediate status of an operation or other control information. You can access
the bit memory area in bits, bytes, words, or double words. Both read and write access is
permitted for M memory.
