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Digital Modulation
SMIQ
1125.5555.03
E-9
2.114
IMPEDANCE
Selection of input impedance and reference voltage.
50
Ω
/GND should be selected for higher clock rates.
Setting 50
Ω
/-2V is suitable for sources with ECL
output. Make sure to select a suitable setting for the
high/low threshold under TRESHOLD.
IEC/IEEE-bus command
:SOUR:DM:INP:IMP G1K
CLOCK SLOPE
Selection of polarity of active edge of externally fed
bit clock or symbol clock.
Note:
In the internal clock mode, CLOCK SLOPE
NEG inverts the clock output signals.
IEC/IEEE-bus
:SOUR:DM:CLOC:POL NORM
TRIGGER SLOPE
Selection of polarity of active trigger edge for input
TRIGIN.
IEC/IEEE-bus
:SOUR:DM:TRIG:SLOP POS