SMIQ
Digital Modulation
1125.5555.03
E-9
2.95
2.10.4
Digital Data and Clock output Signals
2.10.4.1 Serial Interfaces DATA, BIT CLOCK and SYMBOL CLOCK
The following figure shows an example for the output signals at the serial interface for QPSK modulation
(2 bits per symbol). A positive CLOCK EDGE is assumed to be set. The following list containing 4
symbols (8 bits) was used as a data source.
SELECT LIST...
DLIST00
EDIT DATA LIST...
-BIT-------------------------DATA----------------------
00000001
0001 1011
BIT CLOCK (output)
SYMBOL CLOCK (output)
DATA (output)
Data Symbols
00
01
10
11
MSB
LSB
2.10.4.2 Parallel Interfaces DATA and SYMBOL CLOCK
The following figure shows an example for the output signals at the parallel interface. A positive CLOCK
EDGE is assumed to be set.
SYMBOL CLOCK (output)
DATA D7, MSB (output)
2.10.5
External Modulation Data and Control Signals
Digital modulation signals such as data, clock and signals for envelope control can be externally applied
to the modulation coder either via the parallel PAR DATA interface at the rear of SMIQ or via the serial
interface with BNC connectors DATA, BIT CLOCK and SYMBOL CLOCK. Moreover, the asynchronous
serial interface SERDATA can be used. For a detailed description of the interface hardware see Section
Elements at the Rear Panel".
The data source is selected in menu DIGITAL MOD - SOURCE. The clock source is selected in menu
DIGITAL MOD - CLOCK irrespective of the data source selection. The polarity of the active clock edge
can be changed via DIGITAL MOD - EXT INPUTS - CLOCK SLOPE.
