General Purpose Input/Output (GPIO)
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A timing diagram of the debounce circuitry is shown in Fig 8-6.
Fig 8-6 Debounce timing with asynchronous reset Flip-Flops
When input interrupt signals are debounced using a debounce clock, the signals must be active for a minimum of two cycles of the debounce
clock to guarantee that they are registered. Any input pulse widths less than a debounce clock period are bounced. A pulse width between one
and two debounce clock widths may or may not propagate, depending on its phase relationship to the debounce clock. If the input pulse
spans two rising edges of the debounce clock, it is registered. If it spans only one rising edge, it is not registered.
The timing diagram in Fig 8-6 shows both cases: the input signal being bounced, and later, a propagated input signal. If GPIO supports
debounce, then debouncing input signals on Port A can be enabled or disabled under software control.
The dbclk_res_n signal is asynchronously asserted and synchronously de-asserted to the debounce clock, dbclk. The system reset signal,
presetn, is asynchronously asserted and synchronously de-asserted to pclk; synchronization must be external to the component. The pclk and
dbclk signals are assumed to be asynchronous to each other.
Note
: The use of the debounce circuitry increases interrupt latency by two clock cycles of the debounce clock.
The debounce circuitry works with only asynchronous reset flip-flops.
8.2.2.2
Synchronization of Interrupt Signals to System Clock
Interrupt signals can be internally synchronized to a system clock, pclk_intr. Synchronization to pclk_intr must occur for edge-detect signals.
Edge-detected interrupts to the processor are always synchronous to the system bus clock. With level-sensitive interrupts, synchronization is
optional and under software control.
The pclk_intr signal is needed for systems that may have the GPIO pclk bus clock gated off, but the system still wants to detect interrupts. It is
assumed that this clock is synchronous to pclk. If interrupt detection is required only when pclk is running, then pclk_intr and pclk can be
connected to the same clock source. If the system employs a gated pclk to the gpio, pclk_intr needs to be running for interrupt detection to
occur.
The gpio_intrclk_en output signal is asserted when either edge-sensitive interrupts or level-sensitive interrupts requiring synchronization are
enabled in the GPIO block. Both cases require a clock for detection. Therefore, this signal can cause the external clock generator block to
generate pclk_intr.
8.2.2.3
Interrupt Edge Detection
8.2.2.3.1
Single Edge
Fig 8-7 shows an RTL diagram of the synchronization and edge detection of interrupt sources on gpio_ext_porta
N
signals, when
GPIO_INT_BOTH_EDGE=0.
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