Ameba-D User Manual
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(4)
Write data to the data register (DR)
(5)
The SPI slave is now ready for the serial transfer. The transfer begins when the SPI slave is selected by a serial-master device.
(6)
When the transfer is underway, the BUSY status can be polled to return the transfer status. If a transmit FIFO empty interrupt request is
made, write the transmit FIFO (write DR). If a receive FIFO full interrupt request is made, read the receive FIFO (read DR).
(7)
The transfer ends when the serial master removes the select input to the SPI slave. When the transfer is completed, the BUSY status is
reset to 0.
(8)
Disable the SPI slave by writing 0 to SSIENR.
19.2.4
DMA Controller Interface
The SPI has optional built-in DMA capability which can be selected at configuration time; it has a handshaking interface to a DMA Controller to
request and control transfers. The APB bus is used to perform the data transfer to or from the DMA.
The SPI uses two DMA channels, one for the transmit data and one for the receive data. The SPI has these DMA registers:
– Control register to enable DMA operation.
– Register to set the transmit the FIFO level at which a DMA request is made.
– Register to set the receive FIFO level at which a DMA request is made.
To enable the DMA Controller interface on the SPI, you must write the DMA Control Register (DMACR). Writing a 1 into the TDMAE bit field of
DMACR enables the SPI transmit handshaking interface. Writing a 1 into the RDMAE bit field of DMACR enables the SPI receive handshaking
interface.
19.2.4.1
Transmit Watermark Level and Transmit FIFO Underflow
During SPI serial transfers, transmit FIFO requests are made to the DMA Controller whenever the number of entries in the transmit FIFO is less
than or equal to the DMA Transmit Data Level Register (DMATDLR) value; this is known as the watermark level. The DMA Controller responds
by writing a burst of data to the transmit FIFO buffer.
Data should be fetched from the DMA often enough for the transmit FIFO to perform serial transfers continuously; that is, when the FIFO
begins to empty another DMA request should be triggered. Otherwise the FIFO will run out of data (underflow). To prevent this condition, the
user must set the watermark level correctly.
19.2.4.2
Receive Watermark Level and Receive FIFO Overflow
During SPI serial transfers, receive FIFO requests are made to the DMA Controller whenever the number of entries in the receive FIFO is at or
above the DMA Receive Data Level Register; that is, 1. This is known as the watermark level. The DMA Controller responds by
fetching a burst of data from the receive FIFO buffer.
Data should be fetched by the DMA often enough for the receive FIFO to accept serial transfers continuously; that is, when the FIFO begins to
fill, another DMA transfer is requested. Otherwise, the FIFO will fill with data (overflow). To prevent this condition, the user must correctly set
the watermark level.
19.3
Registers
This section describes the programmable registers of the SPI.
19.3.1
Register Memory Map
Table 3-2 provides the details of the SPI memory map. All registers in the SPI are addressed at 32-bit boundaries to remain consistent with the
AHB bus. Where the physical size of any register is less than 32-bit wide, the upper unused bits of the 32-bit boundary are reserved. Writing to
these bits has no effect; reading from these bits returns 0.
The base address of SPI0 is 0x4007_8000, and the size is 2K; the base address of SPI1 is 0x4000_E000, and the size is 2K.
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