Direct Memory Access Controller (DMAC)
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The per_clk signal is equal to hclk if the peripheral is an AHB peripheral; it is equal to pclk if the peripheral is an APB peripheral. The burst
transaction request signal, dma_req, and the single status signal, dma_single, are generated in the peripheral of per_clk and sampled by hclk in
the DMAC. The acknowledge signal, dma_ack, is generated in the DMAC of hclk and sampled in the peripheral by per_clk. The handshaking
mechanism between the DMAC and the peripheral supports quasi-synchronous clocks; that is, hclk and per_clk must be phase- aligned, and the
hclk frequency must be a multiple of the per_clk frequency.
In the case where the destination peripheral is an APB peripheral and for the case of buffered writes through an APB bridge, then caution must
be exercised so as not to overflow the destination peripheral FIFO. This can happen when the write is buffered in the APB bridge; that is, the
write completes on the AHB before completing on the APB bus. The following scenario can cause an overflow: the DMAC asserts dma_ack as
soon as the write transaction completes on the AHB. The APB peripheral, on sampling that the acknowledge signal is asserted, de-asserts its
request signal and asserts the request signal one APB clock cycle later, as it senses that there is space in its FIFO. The issue here is that there
could be space for only a single entry that the first buffered write will consume. The initiation of the second transaction may overflow the FIFO.
If the write were not buffered, then the initiation of the second transaction would not occur, as the destination peripheral would sense that its
FIFO was full.
To avoid this, do one of the following:
Do not use buffered writes.
If using buffered writes, then ensure that dma_ack signal from the DMAC is delayed until the write completes to the APB peripheral. One
way may be to route the dma_ack signal through the APB bridge.
Fig 9-8 shows two back-to-back burst transactions at the end of a block transfer where the hclk frequency is twice the pclk frequency; the
peripheral is an APB peripheral. The second burst transaction terminates the block, and dma_finish[0] is asserted to indicate block completion.
Fig 9-8 Back-to-Back burst transactions – hclk = 2*per_clk
There are two things to note when designing the hardware handshaking interface:
Once asserted, the dma_req burst request signal must remain asserted until the corresponding dma_ack signal is received, even if the
condition that generates dma_req in the peripheral is False.
The dma_req signal should be de-asserted when dma_ack is asserted, even if the condition that generates dma_req in the peripheral is
True.
Fig 9-9 shows a single transaction that occurs in the Single Transaction Region. The handshaking loop is as follows:
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