General Purpose Input/Output (GPIO)
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If GPIO_PORTA_SINGLE_CTL = 0, the register will contain one bit for each bit of
the signal. Upon reset in this case, the value of GPIO_DFLT_SRC_A is replicated
across all bits of the signal so that all bits power up with the same operating
mode. Furthermore, the default source of each bit of the signal can subsequently
be changed by writing to the corresponding bit of this register.
This register is not available unless GPIO_HW_PORTA = 1.
Reset Value
:
If GPIO_PORTA_SINGLE_CTL = 1, then the reset value is
GPIO_DFLT_SRC_A
.
If GPIO_PORTA_SINGLE_CTL = 0, then the reset value is
{GPIO_PWIDTH_A{GPIO_DFLT_SRC_A in each bit}}.
8.3.3.4
gpio_swportb_dr
Name:
Port B Data Register
Size:
GPIO_PWIDTH_B
Address offset
: 0x0C
Read/write access
: read/write
Bit
Name
Access
Description
31:
GPIO_PWIDTH_B
Reserved
Read as zero
Reserved
GPIO_PWIDTHB
–1:0
Port B Data Register
R/W
Values written to this register are output on the I/O signals for
Port B if the corresponding data direction bits for Port B are set
to Output mode and the corresponding control bit for Port B is
set to Software mode. The value read back is equal to the last
value written to this register.
Reset Value:
GPIO_SWPORTB_RESET
8.3.3.5
gpio_swportb_ddr
Name:
Port B Data Direction
Size:
GPIO_PWIDTH_B
Address offset
: 0x10
Read/write access
: read/write
Bit
Name
Access
Description
31:
GPIO_PWIDTH_B
Reserved
Read as zero
Reserved
GPIO_PWIDTH_B
–1:0
Port B Data Direction Register
R/W
Values written to this register independently control the
direction of the corresponding data bit in Port B. The default
direction can be configured as input or output after system
reset through the GPIO_DFLT_DIR_B parameter.
0 – Input (default)
1 – Output
Reset Value
:
GPIO_DFLT_DIR_B
8.3.3.6
gpio_swportb_ctl
Name:
Port B Data Source
Size
:
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2019-05-15 10:08:03