Direct Memory Access Controller (DMAC)
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9.2.11
Generating Requests for the AHB Master Bus Interface
Each channel has a source state machine and destination state machine running in parallel. These state machines generate the request inputs
to the arbiter, which arbitrates for the master bus interface (one arbiter per master bus interface).
When the source/destination state machine is granted control of the master bus interface, and when the master bus interface is granted
control of the external AHB bus, then AHB transfers between the peripheral and the DMAC (on behalf of the granted state machine) can take
place.
AHB transfers from the source peripheral or to the destination peripheral cannot proceed until the channel FIFO is ready. For burst transaction
requests and for transfers involving memory peripherals, the criterion for “FIFO readiness” is controlled by the FIFO_MODE field of the CFGx
register.
The definition of FIFO readiness is the same for:
Single transactions
Burst transactions, where CFG
x
.FIFO_MODE = 0
Transfers involving memory peripherals, where CFG
x
.FIFO_MODE = 0
The channel FIFO is deemed ready when the space/data available is sufficient to complete a single AHB transfer of the specified transfer width.
FIFO readiness for source transfers occurs when the channel FIFO contains enough room to accept at least a single transfer of
CTL
x
.SRC_TR_WIDTH width. FIFO readiness for destination transfers occurs when the channel FIFO contains data to form at least a single
transfer of CTL
x
.DST_TR_WIDTH width.
Note
: An exception to FIFO readiness for destination transfers occurs in “FIFO flush mode.” In this mode, FIFO readiness for destination
transfers occurs when the channel FIFO contains data to form at least a single transfer of CTLx.SRC_TR_WIDTH width (and not
CTLx.DST_TR_WIDTH width, as is the normal case). For an explanation of FIFO flush mode, refer to “Example 5”.
When CFG
x
.FIFO_MODE = 1, then the criteria for FIFO readiness for burst transaction requests and transfers involving memory peripherals are
as follows:
A FIFO is ready for a source burst transfer when the FIFO is less than half empty.
A FIFO is ready for a destination burst transfer when the FIFO is greater than or equal to half full.
Exceptions to this “readiness” occur. During these exceptions, a value of CTLx.FIFO_MODE = 0 is assumed. The following are the exceptions:
Near the end of a burst transaction or block transfer – The channel source state machine does not wait for the channel FIFO to be less
than half empty if the number of source data items left to complete the source burst transaction or source block transfer is less than
DMAH_CH
x
_FIFO_DEPTH/2. Similarly, the channel destination state machine does not wait for the channel FIFO to be greater than or
equal to half full, if the number of destination data items left to complete the destination burst transaction or destination block transfer
is less than DMAH_CH
x
_FIFO_DEPTH/2.
In FIFO flush mode – For an explanation of FIFO flush mode, refer to “Example 5”.
When a channel is suspended – The destination state machine does not wait for the FIFO to become half empty to flush the FIFO,
regardless of the value of the FIFO_MODE field.
After receipt of a split/retry response from a source or destination – The AMBA protocol requires that after an AHB master receives a
split/retry response, it must re-issue the transfer that received the split/retry before attempting any other transfer. Therefore, a transfer
is re-issued to the same address that returned the split/retry, regardless of FIFO_MODE, when the DMAC is next granted the AHB bus.
This is repeated until an OKAY response is received on the AHB hresp bus.
When the source/destination peripheral is not memory, the source/destination state machine waits for a single/burst transaction request.
Upon receipt of a transaction request and only if the channel FIFO is “ready” for source/destination AHB transfers, a request for the master bus
interface is made by the source/destination state machine.
Note
: There is one exception to this, which occurs when the destination peripheral is the flow controller and CFGx.FCMODE = 1 (data pre-
fetching is disabled). Then the source state machine does not generate a request for the master bus interface (even if the FIFO is “ready” for
source transfers and has received a source transaction request) until the destination requests new data. Refer to “Example 8”.
When the source/destination peripheral is memory, the source/destination state machine must wait until the channel FIFO is “ready.” A
request is then made for the master bus interface. There is no handshaking mechanism employed between a memory peripheral and the
DMAC.
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2019-05-15 10:08:03
