CHAPTER 20 ELECTRICAL SPECIFICATIONS
User’s Manual U13850EJ6V0UD
616
(b) Clock asynchronous (T
A
= –40 to +85
°°°°
C, V
DD
= 4.0 to 5.5 V, BV
DD
= 3.0 to 4.0 V, EV
DD
= 3.0 to 5.5 V,
V
SS
= AV
SS
= BV
SS
= EV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to ASTB
↓
)
<10>
t
SAST
0.5T
– 20
ns
Note 1
0.5T
– 20
ns
Address hold time (from ASTB
↓
)
<11>
t
HSTA
Note 2
0.5T
– 22
ns
Address float delay time from DSTB
↓
<12>
t
FDA
0
ns
Data input setup time from address
<13>
t
SAID
(2 + n)T – 50
ns
Data input setup time from DSTB
↓
<14>
t
SDID
(1 + n)T – 50
ns
Delay time from ASTB
↓
to DSTB
↓
<15>
t
DSTD
0.5T
– 15
ns
Data input hold time (from DSTB
↑
)
<16>
t
HDID
0
ns
Address output time from DSTB
↑
<17>
t
DDA
(1 + i)T – 15
ns
Delay time from DSTB
↑
to ASTB
↑
<18>
t
DDST1
0.5T – 15
ns
Delay time from DSTB
↑
to ASTB
↓
<19>
t
DDST2
(1.5 + i)T – 15
ns
DSTB low-level width
<20>
t
WDL
(1 + n)T – 35
ns
ASTB high-level width
<21>
t
WSTH
T – 15
ns
Data output time from DSTB
↓
<22>
t
DDOD
10
ns
Data output setup time (to DSTB
↑
)
<23>
t
SODD
(1 + n)T – 35
ns
Data output hold time (from DSTB
↑
)
<24>
t
HDOD
T – 25
ns
<25>
t
SAWT1
n
≥
1
1.5T – 55
ns
WAIT setup time (to address)
<26>
t
SAWT2
n
≥
1
(1.5 + n)T – 55
ns
<27>
t
HAWT1
n
≥
1
(0.5 + n)T
ns
WAIT hold time (from address)
<28>
t
HAWT2
n
≥
1
(1.5 + n)T
ns
<29>
t
SSTWT1
n
≥
1
T – 45
ns
WAIT setup time (to ASTB
↓
)
<30>
t
SSTWT2
n
≥
1
(1 + n)T – 45
ns
<31>
t
HSTWT1
n
≥
1
nT
ns
WAIT hold time (from ASTB
↓
)
<32>
t
HSTWT2
n
≥
1
(1 + n)T
ns
HLDRQ high-level width
<33>
t
WHQH
T + 10
ns
HLDAK low-level width
<34>
t
WHAL
T – 25
ns
Bus output delay time from HLDAK
↑
<35>
t
DHAC
–6
ns
Delay time from HLDRQ
↓
to HLDAK
↓
<36>
t
DHQHA1
(2n + 7.5)T + 25
ns
Delay time from HLDRQ
↑
to HLDAK
↑
<37>
t
DHQHA2
0.5T
1.5T + 25
ns
Notes 1.
µ
PD703031A, 703031AY, 703031B, 703031BY, 703033A, 703033AY, 703033B, 703033BY, 703034A,
703034AY, 703034B, 703034BY, 703035A, 703035AY, 703035B, 703035BY, 70F3033A, 70F3033AY,
70F3033B, 70F3033BY, 70F3035A, 70F3035AY, 70F3035B, 70F3035BY
2.
µ
PD703030B, 703030BY, 703032A, 703032AY, 703032B, 703032BY, 703036H, 703036HY, 703037A,
703037AY, 703037H, 703037HY, 70F3030B, 70F3030BY, 70F3032A, 70F3032AY, 70F3032B,
70F3032BY, 70F3036H, 70F3036HY, 70F3037A, 70F3037AY, 70F3037H, 70F3037HY
Remarks 1.
T = 1/f
CPU
(f
CPU
: CPU operating clock frequency)
2.
n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3.
i: Number of idle states inserted after a read cycle (0 or 1).
4.
The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from
X1.
Содержание V850/SB1
Страница 2: ...User s Manual U13850EJ6V0UD 2 MEMO ...