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CHAPTER 10 SERIAL INTERFACE FUNCTION
User’s Manual U13850EJ6V0UD
405
(4) Baud rate generator mode control registers n0, n1 (BRGMCn0, BRGMCn1)
These registers set the UARTn source clock.
BRGMCn0 and BRGMCn1 are set by an 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
After reset:
00H
R/W
Address: FFFFF30EH, FFFFF31EH
7
6
5
4
3
2
1
0
BRGMCn0
0
0
0
0
0
TPSn2
TPSn1
TPSn0
(n = 0, 1)
After reset:
00H
R/W
Address: FFFFF320H, FFFFF322H
7
6
5
4
3
2
1
0
BRGMCn1
0
0
0
0
0
0
0
TPSn3
(n = 0, 1)
TPSn3
TPSn2
TPSn1
TPSn0
8-bit counter source clock selection
m
0
0
0
0
External clock (ASCKn)
−
0
0
0
1
f
XX
0
0
0
1
0
f
XX
/2
1
0
0
1
1
f
XX
/4
2
0
1
0
0
f
XX
/8
3
0
1
0
1
f
XX
/16
4
0
1
1
0
f
XX
/32
5
0
1
1
1
at n = 0: TM3 output
at n = 1: TM2 output
−
1
0
0
0
f
XX
/64
6
1
0
0
1
f
XX
/128
7
1
0
1
0
f
XX
/256
8
1
0
1
1
f
XX
/512
9
1
1
0
0
–
1
1
0
1
–
1
1
1
0
–
1
1
1
1
Setting prohibited
–
Cautions 1. If write is performed to BRGMCn0, n1 during communication processing, the output of the
baud rate generator will be disturbed and communication will not be performed normally.
Therefore, do not write to BRGMCn0, n1 during communication processing.
2. Be sure to set bits 7 to 3 of the BRGMCn0 to 0.
Remarks 1.
f
SCK
: Source clock of 8-bit counter
2.
When the output of the timer is selected as the clock, it is not necessary to set the P26/TO2/TI2 and
P27/TO3/TI3 pins in the timer output mode.
Содержание V850/SB1
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