CHAPTER 7 TIMER/COUNTER FUNCTION
User’s Manual U13850EJ6V0UD
237
(1) Timer clock selection registers 20 to 71 and 21 to 71 (TCL20 to TCL70 and TCL21 to TCL71)
These registers set the count clock of timer n.
TCLn0 and TCLn1 are set by an 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
After reset: 00H
R/W
Address: FFFFF244H, FFFFF254H
7
6
5
4
3
2
1
0
TCLn0
0
0
0
0
0
TCLn2
TCLn1
TCLn0
(n = 2, 3)
After reset: 00H
R/W
Address: FFFFF24EH, FFFFF25EH
7
6
5
4
3
2
1
0
TCLn1
0
0
0
0
0
0
0
TCLn3
(n = 2, 3)
Count clock selection
f
XX
TCLn3
TCLn2
TCLn1
TCLn0
Count clock
20 MHz
Note
12.58 MHz
0
0
0
0
TIn falling edge
−
−
0
0
0
1
TIn rising edge
−
−
0
0
1
0
f
XX
/4
200 ns
318 ns
0
0
1
1
f
XX
/8
400 ns
636 ns
0
1
0
0
f
XX
/16
800 ns
1.3
µ
s
0
1
0
1
f
XX
/32
1.6
µ
s
2.5
µ
s
0
1
1
0
f
XX
/128
6.4
µ
s
10.2
µ
s
0
1
1
1
f
XX
/512
25.6
µ
s
40.7
µ
s
1
0
0
0
Setting prohibited
−
−
1
0
0
1
Setting prohibited
−
−
1
0
1
0
f
XX
/64
3.2
µ
s
5.1
µ
s
1
0
1
1
f
XX
/256
12.8
µ
s
20.3
µ
s
1
1
0
0
Setting prohibited
−
−
1
1
0
1
Setting prohibited
−
−
1
1
1
0
Setting prohibited
−
−
1
1
1
1
Setting prohibited
−
−
Note
Only in the V850/SB1.
Cautions 1.
When TCLn0 and TCLn1 are overwritten by different data, write after temporarily
stopping the timer.
2.
Always set bits 3 to 7 to in TCLn0 to 0, and bits 1 to 7 in TCLn1 to 0.
Remark
When connected in cascade, the settings of TCL33 to TCL30 of TM3 are invalid.
Содержание V850/SB1
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